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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 7470 SERIES
Group
User's Manual
keep safety first in your circuit designs ! q Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials q These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. q Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. q All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. q Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. q The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. q If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of JAPAN and/or the country of destination is prohibited. q Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Table of contents
Table of contents
CHAPTER 1. HARDWARE
1.1 1.2 1.3 1.4 1.5 1.6 1.7 Description .............................................................................................................................. 1-2 Group expansion ................................................................................................................... 1-3 Performance overview .......................................................................................................... 1-6 Pin configuration ................................................................................................................. 1-10 Pin description ..................................................................................................................... 1-14 Functional block diagram .................................................................................................. 1-17 Central processing unit (CPU) .........................................................................................1-23 1.7.1 Accumulator (A) ........................................................................................................... 1-24 1.7.2 Index register X (X), Index register Y (Y) .............................................................. 1-24 1.7.3 Stack pointer (S) ......................................................................................................... 1-24 1.7.4 Program counter (PC)................................................................................................. 1-26 1.7.5 Processor status register (PS) ..................................................................................1-26 1.8 Access area .......................................................................................................................... 1-28 1.8.1 Zero page (Addresses 000016 to 00FF16) .............................................................. 1-29 1.8.2 Special page (Addresses FF0016 to FFFF16) ........................................................ 1-29 1.9 Memory allocation ............................................................................................................... 1-30 1.10.1 I/O port ....................................................................................................................... 1-35 1.10.2 Port block diagram .................................................................................................... 1-40 1.10.3 Notes on use ............................................................................................................. 1-45 1.11 Interrupts ............................................................................................................................... 1-48 1.11.1 Description of interrupt source ............................................................................... 1-48 1.11.2 Operation description ................................................................................................ 1-52 1.11.3 Interrupt control ......................................................................................................... 1-55 1.11.4 Notes on use ............................................................................................................. 1-57 1.11.5 Related registers ....................................................................................................... 1-59 1.12 Timers ..................................................................................................................................... 1-62 1.12.1 Operation description ................................................................................................ 1-64 1.12.2 Description of modes ................................................................................................ 1-65 1.12.3 Input latch function ................................................................................................... 1-79 1.12.4 Updating of contents of Timer and Timer latch ................................................... 1-80 1.12.5 Notes on use ............................................................................................................. 1-82 1.12.6 Related registers ....................................................................................................... 1-83 1.13 Serial I/O ................................................................................................................................ 1-89 1.13A 7470/7471 group part .............................................................................................. 1-90 1.13A.1 Operation description ............................................................................................. 1-90 1.13A.2 Byte specification mode .........................................................................................1-98 1.13A.3 Pins ......................................................................................................................... 1-101 1.10 I/O pins .................................................................................................................................. 1-35
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1.13A.4 Notes on use ......................................................................................................... 1-101 1.13A.5 Related registers ...................................................................................................1-102 1.13B 7477/7478 group part ........................................................................................... 1-105 1.13B.1 Operation description .......................................................................................... 1-105 1.13B.2 Pins ......................................................................................................................... 1-127 1.13B.3 Notes on use ......................................................................................................... 1-128 1.13B.4 Related registers ...................................................................................................1-131 1.14 A-D converter ..................................................................................................................... 1-139 1.14.1 A-D conversion method ......................................................................................... 1-140 1.14.2 Pins ........................................................................................................................... 1-144 1.14.3 Notes on use ........................................................................................................... 1-144 1.14.4 References ............................................................................................................... 1-145 1.14.5 Related registers .....................................................................................................1-147 1.15 Reset ..................................................................................................................................... 1-149 1.15.1 Operation description ............................................................................................. 1-149 1.15.2 Internal status immediately after reset release ................................................. 1-151 1.15.3 Notes on use ........................................................................................................... 1-152 1.16 Oscillation circuit .............................................................................................................. 1-153 1.16.1 Oscillation circuit .....................................................................................................1-153 1.16.2 Sub-clock oscillation circuit ................................................................................... 1-155 1.16.3 Oscillation operation ...............................................................................................1-156 1.16.4 Oscillation stabilizing time ..................................................................................... 1-158 1.16.5 Notes on use ........................................................................................................... 1-159 1.17 Low-power dissipation function .................................................................................... 1-160 1.17.1 Stop mode ................................................................................................................ 1-162 1.17.2 Wait mode ................................................................................................................ 1-166 1.17.3 Notes on use ........................................................................................................... 1-169 1.17.4 Related register .......................................................................................................1-170 1.18 State transitions ................................................................................................................ 1-171 1.19 Built-in PROM version ......................................................................................................1-175 1.19.1 EPROM mode .......................................................................................................... 1-176 1.19.2 Pin description ......................................................................................................... 1-182 1.19.3 Writing, reading, and erasing to built-in PROM ................................................ 1-185 1.19.4 Notes on use ........................................................................................................... 1-186 1.20 Emulator MCU .................................................................................................................... 1-188 1.21 Electrical characteristics .................................................................................................1-189 1.21.1 Electrical characteristics ........................................................................................ 1-189 1.21.2 Timing requirements, switching characteristics .................................................. 1-201 1.21.3 Power source current standard characteristics .................................................. 1-203 1.21.4 Port standard characteristics ................................................................................ 1-208 1.21.5 A-D conversion standard characteristics ............................................................ 1-213
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7470/7471/7477/7478 GROUP USER'S MANUAL
Table of contents CHAPTER 2. APPLICATION
2.1 I/O pins .................................................................................................................................... 2-2 2.1.1 I/O port ........................................................................................................................... 2-2 2.1.2 Notes on use ................................................................................................................. 2-5 2.2 Interrupts ................................................................................................................................. 2-7 2.2.1 Memory allocation ......................................................................................................... 2-7 2.2.2 Processor status register (PS) .................................................................................... 2-8 2.2.3 Application example ...................................................................................................... 2-9 2.2.4 Notes on use ................................................................................................................. 2-9 2.3 Timers ..................................................................................................................................... 2-10 2.3.1 Memory allocation ....................................................................................................... 2-10 2.3.2 Application example .................................................................................................... 2-11 2.3.3 Notes on use ............................................................................................................... 2-22 2.4 Serial I/O ................................................................................................................................ 2-23 2.4.1 7470/7471 group memory allocation ....................................................................... 2-23 2.4.2 Application example .................................................................................................... 2-24 2.4.3 7477/7478 group memory allocation ....................................................................... 2-29 2.4.4 Application examples .................................................................................................. 2-30 2.4.5 Notes on use ............................................................................................................... 2-34 2.5 A-D converter ....................................................................................................................... 2-35 2.5.1 Memory allocation ....................................................................................................... 2-35 2.5.2 Application examples .................................................................................................. 2-36 2.5.3 Notes on use ............................................................................................................... 2-38 2.6 Reset ....................................................................................................................................... 2-39 2.6.1 Reset circuit ................................................................................................................. 2-39 2.6.2 Notes on use ............................................................................................................... 2-39 2.7 2.8 Oscillation circuit ................................................................................................................ 2-40 Low-power dissipation function ....................................................................................... 2-41 2.8.1 CPU mode register ..................................................................................................... 2-41 2.8.2 Application examples .................................................................................................. 2-42 2.8.3 Notes on use ............................................................................................................... 2-47 2.9 Countermeasures against noise ......................................................................................2-48 2.9.1 Shortest wiring length ................................................................................................. 2-48 2.9.2 Connection of a bypass capacitor across the VSS line and the VCC line ......... 2-51 2.9.3 Wiring to analog input pins........................................................................................ 2-51 2.9.4 Consideration for oscillator ........................................................................................ 2-52 2.9.5 Setup for I/O ports ...................................................................................................... 2-53 2.9.6 Providing of watchdog timer function by software ................................................ 2-54 2.10 Notes on programming ...................................................................................................... 2-56 2.10.1 Processor status register .........................................................................................2-56 2.10.2 Decimal calculations ................................................................................................. 2-57 2.11 Differences between 7470/7471 group and 7477/7478 group .................................. 2-58
7470/7471/7477/7478 GROUP USER'S MANUAL
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Table of contents
2.12 Example of application circuit .........................................................................................2-59
CHAPTER 3. APPENDIX
3.1 3.2 3.3 3.4 3.5 3.6 3.7 Control registers .................................................................................................................... 3-2 Mask ROM ordering method ............................................................................................. 3-14 ROM programming ordering method ............................................................................. 3-46 Mark specification form ..................................................................................................... 3-62 Package outline ................................................................................................................... 3-67 SFR memory map ................................................................................................................ 3-69 Pin configuration ................................................................................................................. 3-70
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7470/7471/7477/7478 GROUP USER'S MANUAL
CHAPTER 1 HARDWARE
1.1 Description 1.2 Group expansion 1.3 Performance overview 1.4 Pin configuration 1.5 Pin description 1.6 Functional block diagram 1.7 Central processing unit (CPU) 1.8 Access area 1.9 Memory allocation 1.10 I/O pins 1.11 Interrupts 1.12 Timers 1.13 Serial I/O 1.14 A-D converter 1.15 Reset 1.16 Oscillation circuit 1.17 Low-power dissipation function 1.18 State transitions 1.19 Built-in PROM version 1.20 Emulator MCU 1.21 Electrical characteristics
HARDWARE
1.1 Description
1.1 Description
The 7470/7471/7477/7478 group is an 8-bit single-chip microcomputer which utilizes a silicon gate CMOS processing and has a simple instruction system of the 740 family using the same memory space for ROM, RAM and I/O.
1-2
7470/7471/7477/7478 GROUP USER'S MANUAL
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1.2 Group expansion
1.2 Group expansion
The 7470/7471/7477/7478 group develops with the M37470M2-XXXSP as the base chip in the 7470 series. The classification of the 7470 series is as follows. 7470 series 7470 7471 7477 7478 7480 7481 group group group group group** group**
**:Under development
In this manual, when multiple models are described collectively, their names are arranged by putting "/" among them for separation. 7470 group, 7471 group 7470/7471 group 7477 group, 7478 group 7477/7478 group 7470 group, 7477 group 7470/7477 group 7471 group, 7478 group 7471/7478 group
The 7470/7471/7477/7478 group permits group expansion as shown in Figure 1.2.1. This group expansion is all performed only by differences in memory type and capacity and the number of ports. This allows the user to select optimum elements according to the user's system. The 7470/7471/7477/7478 group supports the following in addition to the mask ROM version. (1) Support of One Time PROM version The One Time PROM version is a programmable microcomputer and can perform a one-time write operation to the built-in programmable ROM (PROM). For the details, refer to "1.19 Built-in PROM version." (2) Support of EPROM version (with window) The built-in EPROM version is a programmable microcomputer with window and can perform write and erase operations to the built-in EPROM. For the details, refer to "1.19 Built-in PROM version." (3) Support of emulator MCU The emulator MCU is a microcomputer designed for program development which facilitates program development and is an optimum element for system evaluation. For the details, refer to"1.20 Emulator MCU." Table 1.2.1 shows the products which the 7470/7471/7477/7478 group supports.
7470/7471/7477/7478 GROUP USER'S MANUAL
1-3
HARDWARE
1.2 Group expansion
* Memory Expansion Plan of 7470/7471 group
ROM size (bytes) 16K M37470M8/E8-XXXSP M37471M8/E8-XXXSP/FP M37471E8SS
12K
8K
M37470M4/E4-XXXSP M37471M4/E4-XXXSP/FP
4K
M37470M2-XXXSP M37471M2-XXXSP/FP
0
128
192
256
384
RAM size (bytes)
* Memory Expansion Plan of 7477/7478 group
ROM size (bytes) 16K M37477M8/E8-XXXSP/FP M37477M8T/E8TXXXSP/FP M37478M8/E8-XXXSP/FP M37478M8T/E8TXXXSP/FP M37478E8SS
12K M37477M4-XXXSP/FP M37477M4TXXXSP/FP M37478M4-XXXSP/FP M37478M4TXXXSP/FP M37477M2TXXXSP/FP M37478M2TXXXSP/FP
8K
4K
0
128
192
256
384
RAM size (bytes)
: Mass product : New product : Under development
Fig. 1.2.1 Memory expansion plan of 7470/7471/7477/7478 group
(As of July 1996)
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7470/7471/7477/7478 GROUP USER'S MANUAL
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1.2 Group expansion
Table 1.2.1 List of supported products Product M37470M2-XXXSP M37470M4-XXXSP M37470E4-XXXSP M37470M8-XXXSP M37470E8-XXXSP M37471M2-XXXSP M37471M2-XXXFP M37471M4-XXXSP M37471M4-XXXFP M37471E4-XXXSP M37471E4-XXXFP M37471M8-XXXSP M37471M8-XXXFP M37471E8-XXXSP M37471E8-XXXFP M37471E8SS M37471RSS M37477M2TXXXSP M37477M2TXXXFP M37477M4-XXXSP M37477M4-XXXFP M37477M4TXXXSP M37477M4TXXXFP M37477M8-XXXSP M37477M8-XXXFP M37477M8TXXXSP M37477M8TXXXFP M37477E8-XXXSP M37477E8-XXXFP M37477E8TXXXSP M37477E8TXXXFP M37478M2TXXXSP M37478M2TXXXFP M37478M4-XXXSP M37478M4-XXXFP M37478M4TXXXSP M37478M4TXXXFP M37478M8-XXXSP M37478M8-XXXFP M37478M8TXXXSP M37478M8TXXXFP M37478E8-XXXSP M37478E8-XXXFP M37478E8TXXXSP M37478E8TXXXFP M37478E8SS M37478RSS ROM RAM I/O Port (bytes) (bytes) 4096 128 I/O ports: 22 (Including 4 analog 8192 192 input pins.) 16384 384 Input ports: 4 4096 128 Package (As of July 1996) Remarks Mask ROM version 32P4B One Time PROM version Mask ROM version One Time PROM version Mask ROM version
8192
192
16384
384
42P4B 56P6N-A 42P4B 56P6N-A 42P4B I/O ports: 28 (Including 8 analog 56P6N-A 42P4B input pins.) 56P6N-A Input ports: 8 42P4B 56P6N-A 42S1B-A 42S1M 32P4B 32P2W-A 32P4B 32P2W-A 32P4B I/O ports: 18 32P2W-A Input ports: 8 32P4B (Including 4 analog 32P2W-A input pins.) 32P4B 32P2W-A 32P4B 32P2W-A 32P4B 32P2W-A 42P4B 56P6N-A 42P4B 56P6N-A 42P4B I/O ports: 20 56P6N-A Input ports: 16 42P4B (Including 8 analog 56P6N-A 42P4B input pins.) 56P6N-A 42P4B 56P6N-A 42P4B 56P6N-A I/O ports: 20 42S1B-A Input ports: 16 (Including 8 analog 42S1M input pins.)
One Time PROM version Mask ROM version One Time PROM version EPROM version Emulator MCU Mask ROM version* Mask ROM version Mask ROM version* Mask ROM version Mask ROM version* One Time PROM version One Time PROM version* Mask ROM version* Mask ROM version Mask ROM version* Mask ROM version Mask ROM version* One Time PROM version One Time PROM version* EPROM version Emulator MCU
63.5K (Note) 4096
384 128
8192
192
16384
384
4096
128
8192
192
16384
384
16384 63.5K (Note)
384 384
Note: Address space usable as a ROM area.
*
: Extended operating temperature version.
7470/7471/7477/7478 GROUP USER'S MANUAL
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HARDWARE
1.3 Performance overview
1.3 Performance overview
Tables 1.3.1 to 1.3.4 show the performance overview of 7470/7471/7477/7478 group. Table 1.3.1 Performance overview of 7470 group Functions Parameter 71 (69 basic instructions of 740 family and 2 multiplication Number of basic instructions and division instructions) 0.5 s (the minimum instructions, at 8 MHz clock input Instruction execution time oscillation frequency) Clock input oscillation frequency 8 MHz (max.) 4096 bytes M37470M2 8192 bytes ROM M37470M4/E4 Memory 16384 bytes M37470M8/E8 size 128 bytes M37470M2 192 bytes RAM M37470M4/E4 384 bytes M37470M8/E8 8-bit P0 Input/ 8-bit P1 I/O Output 4-bit P2 port 2-bit P4 4-bit Input P3 8-bit ! 1 Serial I/O 8-bit timer ! 4 Timers 1 (in common with 2 timer) PWM 8-bit ! 1 (4 channels) A-D converter 64 levels max. M37470M2 96 levels max. Subroutine nesting M37470M4/E4 192 levels max. M37470M8/E8 5 external interrupts, 6 internal interrupts, 1 software interrupt Interrupt Built-in circuit with internal feedback resistor (an external Clock generating circuit ceramic resonator or a quartz-crystal oscillator) 2.7 V to 4.5 V (at (2.2 VCC-2) MHz clock input oscillation frequency) Power source voltage 4.5 V to 5.5 V (at 8 MHz clock input oscillation frequency) 35 mW typ. Power dissipation (at 8 MHz clock input oscillation frequency) Input/Output withstand voltage 5 V Input/Output Output current characteristics -5 mA to +10 mA (P0, P1, P2, P4: CMOS 3-state) Operating temperature -20 C to +85 C Device structure CMOS silicon gate Package 32-pin shrink plastic molded DIP M37470Mx/Ex-XXXSP
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1.3 Performance overview
Table 1.3.2 Performance overview of 7471 group Functions 71 (69 basic instructions of 740 family and 2 multiplication Number of basic instructions and division instructions) 0.5 s (the minimum instructions, at 8 MHz clock input Instruction execution time oscillation frequency) Clock input oscillation frequency 8 MHz (max.) M37471M2 4096 bytes M37471M4/E4 8192 bytes ROM Memory M37471M8/E8 16384 bytes size M37471M2 128 bytes RAM M37471M4/E4 192 bytes M37471M8/E8 384 bytes P0 8-bit P1 8-bit Input/ I/O P2 8-bit Output P4 4-bit port P3 4-bit Input P5 4-bit 8-bit ! 1 Serial I/O Timers 8-bit timer ! 4 PWM 1 (in common with 2 timer) A-D converter 8-bit ! 1 (8 channels) M37471M2 64 levels max. Subroutine nesting M37471M4/E4 96 levels max. M37471M8/E8 192 levels max. Interrupt 5 external interrupts, 6 internal interrupts, 1 software interrupt Built-in circuit with internal feedback resistor (an external Clock generating circuit ceramic resonator or a quartz-crystal oscillator) Built-in circuit with internal feedback resistor (a guartzSub-clock generating circuit crystal oscillator) 2.7 V to 4.5 V (at (2.2 VCC-2) MHz clock input oscillation frequency) Power source voltage 4.5 V to 5.5 V (at 8 MHz clock input oscillation frequency) 35 mW typ. Power dissipation (at 8 MHz clock input oscillation frequency) Input/Output withstand voltage 5 V Input/Output Output current characteristics -5 mA to +10 mA (P0, P1, P2, P4: CMOS 3-state) Operating temperature -20 C to +85 C Device structure CMOS silicon gate 42-pin shrink plastic molded DIP M37471Mx/Ex-XXXSP Package 56-pin plastic molded QFP M37471Mx/Ex-XXXFP 42-pin shrink ceramic DIP M37471E8SS Parameter
7470/7471/7477/7478 GROUP USER'S MANUAL
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HARDWARE
1.3 Performance overview
Table 1.3.3 Performance overview of 7477 group Parameter Functions 71 (69 basic instructions of 740 family and 2 multiplication Number of basic instructions and division instructions) 0.5 s (the minimum instructions, at 8 MHz clock input Instruction execution time oscillation frequency) 8 MHz (max.) Clock input oscillation frequency M37477M2 4096 bytes M37477M4 8192 bytes ROM Memory M37477M8/E8 16384 bytes size M37477M2 128 bytes M37477M4 192 bytes RAM M37477M8/E8 384 bytes P0 8-bit I/O Input/ P1 8-bit Output P4 2-bit port P2 4-bit Input P3 4-bit 8-bit ! 1 (operable in UART mode) Serial I/O 8-bit timer ! 4 Timers 1 (in common with 2 timer) PWM 8-bit ! 1 (4 channels) A-D converter 64 level max. M37477M2 96 level max. Subroutine nesting M37477M4 192 level max. M37477M8/E8 5 external interrupts, 7 internal interrupts, 1 software interrupt Interrupt Built-in circuit with internal feedback resistor (an external Clock generating circuit ceramic resonator or a quartz-crystal oscillator) 2.7 V to 4.5 V (at (2.2 VCC-2) MHz clock input oscillation frequency) Power source voltage 4.5 V to 5.5 V (at 8 MHz clock input oscillation frequency) 35 mW typ. Power dissipation (at 8 MHz clock input oscillation frequency) Input/Output Input/Output withstand voltage 5 V -5 mA to +10 mA (P0, P1, P4: CMOS 3-state) characteristics Output current -20 C to +85 C (-40 C to +85 C for extended operating temperature version) Operating temperature CMOS silicon gate Device structure M37477Mx/E8-XXXSP 32-pin shrink plastic molded DIP M37477Mx/E8TXXXSP Package M37477Mx/E8-XXXFP 32-pin plastic molded SOP M37477Mx/E8TXXXFP
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1.3 Performance overview
Table 1.3.4 Performance overview of 7478 group Functions 71 (69 basic instructions of 740 family and 2 multiplication Number of basic instructions and division instructions) 0.5 s (the minimum instructions, at 8 MHz clock input Instruction execution time oscillation frequency) 8 MHz (max.) Clock input oscillation frequency 4096 bytes M37478M2 8192 bytes ROM M37478M4 Memory 16384 bytes M37478M8/E8 size 128 bytes M37478M2 192 bytes RAM M37478M4 384 bytes M37478M8/E8 8-bit P0 8-bit I/O P1 Input/ 4-bit P4 Output 8-bit P2 port 4-bit Input P3 4-bit P5 8-bit ! 1 (operable in UART mode) Serial I/O 8-bit timer ! 4 Timers 1 (in common with 2 timer) PWM 8-bit ! 1 (8 channels) A-D converter 64 level max. M37478M2 Subroutine nesting 96 level max. M37478M4 192 level max. M37478M8/E8 Interrupt 5 external interrupts, 7 internal interrupts, 1 software interrupt Built-in circuit with internal feedback resistor (an external Clock generating circuit ceramic resonator or a quartz-crystal oscillator) Built-in circuit with internal feedback resistor (a quartzSub-clock generating circuit crystal oscillator) 2.7 V to 4.5 V (at (2.2 VCC-2) MHz clock input oscillation frequency) Power source voltage 4.5 V to 5.5 V (at 8 MHz clock input oscillation frequency) 35 mW typ. Power dissipation (at 8 MHz clock input oscillation frequency) Input/Output Input/Output withstand voltage 5 V characteristics -5 mA to +10 mA (P0, P1, P4: CMOS 3-state) Output current Operating temperature -20 C to +85 C (-40 C to +85 C for extended operating temperature version) Device structure CMOS silicon gate M37478Mx/E8-XXXSP 42-pin shrink plastic molded DIP M37478Mx/E8TXXXSP Package M37478Mx/E8-XXXFP 56-pin plastic molded QFP M37478Mx/E8TXXXFP M37478E8SS 42-pin shrink ceramic DIP Parameter
7470/7471/7477/7478 GROUP USER'S MANUAL
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HARDWARE
1.4 Pin configuration
1.4 Pin configuration
Figures 1.4.1 to 1.4.4 show a pin configuration of "7470/7471/7477/7478 group." For pin connections in the EPROM mode of the built-in programmable ROM version, refer to "Figures 1.19.1 to 1.19.6 Pin connections in EPROM mode."
PIN CONFIGURATION (TOP VIEW)
P17/SRDY P16/CLK P15/SOUT P14/SIN P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4
32 31 30 29
5 6 7 8 9 10 11 12 13 14 15 16
28 27 26 25 24 23 22 21 20 19 18 17
P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0 RESET VCC
Outline 32P4B (Note)
Note: The M37470M2-XXXSP and M37470M4/E4-XXXSP are included in the 32P4B package. All of these products are pin-compatible.
M37470M8-XXXSP M37470E8-XXXSP
Fig. 1.4.1 Pin configuration of 7470 group
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7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
1.4 Pin configuration
PIN CONFIGURATION (TOP VIEW)
P53 P17/SRDY P16/CLK P15/SOUT P14/SIN P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0
RESET
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
Outline 42P4B (Note 1) 42S1B-A (M37471E8SS)
43
42
38
34
44
39
35
40
36
32
31
30
41
37
33
29
NC P04 P03 P02 P01 P00 P43 P42 P41 P40 NC P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0 NC
M37471M8-XXXSP M37471E8-XXXSP M37471E8SS
P51/XCOUT P50/XCIN VCC
NC P05 P06 P07 P52 NC VSS P53 P17/SRDY P16/CLK P15/SOUT NC
45 46 47 48 49 50 51 52 53 54 55 56 10 12 13 14 15 11 16 3 4 2 1 6 7 8 5 9
28 27 26 25 24
RESET
M37471M8-XXXFP M37471E8-XXXFP
23 22 21 20 19 18 17
NC P51/XCOUT P50/XCIN NC VCC VSS AVSS NC XOUT XIN NC
NC P14/SIN P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF NC
Outline 56P6N-A (Note 2)
NC: No connection
Notes 1 : The M37471M2-XXXSP and M37471M4/E4-XXXSP are included in the 42P4B package. All of these products are pin-compatible. 2 : The M37471M2-XXXFP and M37471M4/E4-XXXFP are included in the 56P6N-A package. All of these products are pin-compatible. 3 : The only differences between the 42P4B package product and the 56P6N-A package product are package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AVSS pin.
Fig. 1.4.2 Pin configuration of 7471 group
7470/7471/7477/7478 GROUP USER'S MANUAL
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HARDWARE
1.4 Pin configuration
PIN CONFIGURATION (TOP VIEW)
P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4
32 31 30 29
5 6 7 8 9 10 11 12 13 14 15 16
28 27 26 25 24 23 22 21 20 19 18 17
P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0
RESET
Outline 32P4B (Note 1)
M37477M8-XXXSP M37477E8-XXXSP M37477M8TXXXSP M37477E8TXXXSP
VCC
P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4
32 31 30 29
5 6 7 8 9 10 11 12 13 14 15 16
28 27 26 25 24 23 22 21 20 19 18 17
P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0
RESET
Outline 32P2W-A (Note 2)
Notes 1 : The M37477M2TXXXSP, M37477M4-XXXSP and M37477M4TXXXSP are included in the 32P4B package. These products are pin-compatible. 2 : The M37477M2TXXXFP, M37477M4-XXXFP and M37477M4TXXXFP are included in the 32P2W-A package. These products are pin-compatible. 3 : The only differences between the 32P4B package product and the 32P2W-A package product are package shape and absolute maximum ratings.
M37477M8-XXXFP M37477E8-XXXFP M37477M8TXXXFP M37477E8TXXXFP
VCC
Fig. 1.4.3 Pin configuration of 7477 group
1-12
7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
1.4 Pin configuration
PIN CONFIGURATION (TOP VIEW)
P53 P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4 5 6 7 42 41 40 39 38 37 36
8 9 10 11 12 13 14 15 16 17 18 19 20 21
35 34 33 32 31 30 29 28 27 26 25 24 23 22
P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0
RESET
Outline 42P4B (Note 1) 42S1B-A (M37478E8SS)
NC P04 P03 P02 P01 P00 P43 P42 P41 P40 NC P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0 NC
41 37 33 43 39 35 31 42 38 34 44 40 36 32 30 29
M37478M8-XXXSP M37478E8-XXXSP M37478M8TXXXSP M37478E8TXXXSP M37478E8SS
P51/XCOUT P50/XCIN VCC
NC P05 P06 P07 P52 NC VSS P53 P17/SRDY P16/SCLK P15/TXD NC
45 46 47 48 49 50 51 52 53 54 55 56
10 14 12 13 11 15 16 3 4 2 1 6 7 8 5 9
28 27 26 25
RESET
M37478M8-XXXFP M37478E8-XXXFP M37478M8TXXXFP M37478E8TXXXFP
24 23 22 21 20 19 18 17
NC P51/XCOUT P50/XCIN NC VCC VSS AVSS NC XOUT XIN NC
NC P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF NC
Outline 56P6N-A (Note 2)
NC: No connection
Notes 1 : The M37478M2TXXXSP, M37478M4-XXXSP and M37478M4TXXXSP are included in the 42P4B package. These products are pin-compatible 2 : The M37478M2TXXXFP, M37478M4-XXXFP and M37478M4TXXXFP are included in the 56P6N-A package. These products are pin-compatible 3 : The only differences between the 42P4B package product and the 56P6N-A package product are package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AVSS pin.
Fig. 1.4.4 Pin configuration of 7478 group
7470/7471/7477/7478 GROUP USER'S MANUAL
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HARDWARE
1.5 Pin description
1.5 Pin description
Tables 1.5.1 to 1.5.3 show a pin description. For pin functions in the EPROM mode of the built-in programmable ROM version, refer to "1.19.2 Pin description." Table 1.5.1 Pin description (1) Pin VCC, VSS Name Power source Input/ Output Functions * Apply the following voltage to the VCC pin: 2.7 V to 4.5 V (at f(XIN) = (2.2 VCC-2) MHz clock input oscillation frequency) or 4.5 V to 5.5 V (at f(XIN) = 8 MHz clock input oscillation frequency). * Apply 0 V to the VSS pin. * Ground level input pin for the A-D converter. * Apply the same voltage as VSS pin to the AVSS pin. Note: This pin is dedicated to 56P6N-A package products among the 7471/7478 group. * Reference voltage input pin for the A-D converter. * When using the A-D converter, apply 0.5 VCC (Q 2) to VCC [V]. * When not using the A-D converter, connect to VCC. * Reset input pin * The microcomputer is put into a reset state by keeping the RESET pin at "L" for 2 s or more, and the reset state is released by returning the RESET pin to "H." * An input pin and an output pin for the main clock generating circuit. * Connect a ceramic resonator or a quartz-crystal oscillator between pins XIN and XOUT. * A feedback resistor is incorporated between the XIN and the XOUT pins. * To use an external clock input, connect the clock oscillation source to the XIN pin and leave the XOUT pin open. * Port P0 is an 8-bit I/O port. * The output structure is CMOS output. * In input mode, a pull-up transistor is connectable in units of one bit. * In input mode, a key-on wake up function is provided.
AVSS
Analog power source
VREF
Reference voltage input
Input
RESET
Reset input
Input
XIN
Clock input
Input
XOUT
Clock output
Output
P00-P07
I/O port P0
I/O
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7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
1.5 Pin description
Table 1.5.2 Pin description (2) Pin P10-P17 Name I/O port P1 Input/ Output I/O Functions * Port P1 is an 8-bit I/O port. * The output structure is CMOS output. * In input mode, pull-up transistor can be connected in units of 4-bit. * Pins P12 and P13 are in common with timer output pins T0, T1 respectively. * In the case of the 7470/7471 group, P14-P17 are in common with serial I/O pins SIN, SOUT, CLK, SRDY respectirely. * In the case of the 7470/7471 group, the outputs of pins SOUT and the SRDY can be N-channel open drain outputs. * In the case of the 7477/7478 group, P14-P17 are in common with serial I/O pins RXD, TXD, SCLK, SRDY, respectively. * Port P2 is an 8-bit I/O port. * The output structure is CMOS output. * In input mode, pull-up transistor can be connected in units of 4-bit. * Pins P20-P27 are in common with analog input pins IN0-IN7 respectively. Note: The 7470 group has only the 4 pins P20-P23 (IN0-IN3). * Port P2 is an 8-bit input port. * It is impossible to connect a pull-up transistor. * Pins P20-P27 are in common with analog lnput pins IN0-IN7 respectively. Note: The 7477 group has only the 4 pins P20-P23 (IN0-IN3). * Port P3 is a 4-bit input port. * Pins P30, P31 are in common with external interrupt input pins INT0, INT1 respectively. * Pins P32, P33 are in common with timer input pins CNTR0, CNTR1 respectively. * Port P4 is a 4-bit I/O port. * The output structure is CMOS output. * In input mode, pull-up transistor can be connected in units of 4-bit. Note: The 7470/7477 group has only 2 pins P40 and P41.
P20-P27
I/O port P2 (7470/7471 group)
I/O
Input port P2 (7477/7478 group)
Input
P30-P33
Input port P3
Input
P40-P43
I/O port P4
I/O
7470/7471/7477/7478 GROUP USER'S MANUAL
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HARDWARE
1.5 Pin description
Table 1.5.3 Pin description (3) Pin P50-P53 Name Input port P5 Input/ Output Input Functions * Port P5 is a 4-bit input port. * Pull-up transistor can be connected in units of 4-bit. * Pins P50, P51 are in common with input/output pins for sub-clock generating circuit XCIN, XCOUT respectively. * When using pins P50 and P51 as pins XCIN and XCOUT, connect a quartz-crystal oscillator between pins XCIN and XCOUT. * When using pins P50 and P51 as pins XCIN and XCOUT, a feedback resistor is connected between pins XCIN and XCOUT. * To use an external clock input, connect the clock oscillation source to the XCIN pin and leave the XCOUT pin open. Note: Only the 7471/7478 group has pins P50-P53.
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7470/7471/7477/7478 GROUP USER'S MANUAL
M37470M8/E8-XXXSP BLOCK DIAGRAM
Clock input XIN VCC
17 16
Clock output XOUT VSS Data bus
Reset input
RESET
14
15
18
Clock generating circuit (Note 2) (Note 1) ROM 16384 bytes Instruction decoder Timer 2(8) Control signal Index register X(8) Index register Y(8) Timer 3(8) Timer 4(8) PWM control Stack pointer S(8) Timer 1(8) Program counter PCH(8) Program counter PCL(8) Instruction register(8) RAM 384 bytes
1.6 Functional block diagram
Fig. 1.6.1 M37470MX/EX-XXXSP functional block diagram
Byte counter(4) INT1 A-D converter Serial I/O(8) 4 P3(4) P2(4) P1(8) P0(8) CNTR0 INT0
The functional block diagram of 7470/7471/7477/7478 group is shown in Figure 1.6.1 to Figure 1.6.6.
7470/7471/7477/7478 GROUP USER'S MANUAL
22 21 20 19 13 9 10 11 12 1 2 3 4 5 6 7 8
8-bit Arithmetic and logical unit
Accumulator A(8)
Processor status register PS(8)
CNTR1
P4(2)
24 23
32 31 30 29 28 27 26 25
VREF Input port P3
Reference voltage input
I/O port P4
I/O port P2
I/O port P1
I/O port P0
HARDWARE
Notes 1 : 4096 bytes for M37470M2-XXXSP, and 8192 bytes for M37470M4/E4-XXXSP 2 : 128 bytes for M37470M2-XXXSP, and 192 bytes for M37470M4/E4-XXXSP
1.6 Functional block diagram
1-17
1-18
Reset input
RESET
M37471M8/E8-XXXSP, M37471E8SS BLOCK DIAGRAM
Clock input XIN VCC
22 21
Clock output XOUT VSS Data bus
25
HARDWARE
19
20
Clock generating circuit (Note 2) RAM ROM 16384 bytes Timer 2(8) Control signal Processor status register PS(8) Index register X(8) Index register Y(8) Timer 3(8) Timer 4(8) PWM control Stack pointer S(8) Timer 1(8) Instruction decoder 384 bytes Program counter PCH(8) Program counter PCL(8) Instruction register(8) (Note 1)
1.6 Functional block diagram
XCIN
XCOUT
8-bit Arithmetic and logical unit
Accumulator A(8)
Byte counter(4) INT1 A-D converter Serial I/O(8) 8 P3(4) P2(8) P1(8) P0(8) CNTR1 CNTR0 INT0
XCOUT
Fig. 1.6.2 M37471MX/EX-XXXSP, M37471E8SS functional block diagram
7470/7471/7477/7478 GROUP USER'S MANUAL
29 28 27 26 18 10 11 12 13 14 15 16 17 2 3 4 5 6 7 8 9
XCIN
P5(4)
P4(4)
1
42 24 23
33 32 31 30
41 40 39 38 37 36 35 34
VREF Input port P3 Reference voltage input I/O port P2 I/O port P1 I/O port P0
Input Port P5
I/O port P4
Notes 1 : 4096 bytes for M37471M2-XXXSP, and 8192 bytes for M37471M4/E4-XXXSP 2 : 128 bytes for M37471M2-XXXSP, and 192 bytes for M37471M4/E4-XXXSP
M37471M8/E8-XXXFP BLOCK DIAGRAM
Clock input XIN Reset input
RESET
Clock output XOUT VCC
23 21 22 51
VSS AVSS Data bus
18 28
19
Clock generating circuit (Note 2) RAM 384 bytes Timer 2(8) Control signal Processor status register PS(8) Index register X(8) Timer 3(8) Timer 4(8) PWM control Index register Y(8) Stack pointer S(8) Program counter PCH(8) Program counter PCL(8) 16384 bytes Timer 1(8) Instruction decoder ROM Instruction register(8) (Note 1)
XCIN
XCOUT
Fig. 1.6.3 M37471MX/EX-XXXFP functional block diagram
Byte counter(4) INT1 A-D converter Serial I/O(8) 8 P3(4) P2(8) P1(8) P0(8) CNTR1 CNTR0 INT0
8-bit Arithmetic and logical unit
Accumulator A(8)
7470/7471/7477/7478 GROUP USER'S MANUAL
33 32 31 30 15 7 8 9 10 11 12 13 14 53 54 55 2 3 4 5 6
XCOUT
XCIN
P5(4)
P4(4)
52 49 26 25
38 37 36 35
48 47 46 43 42 41 40 39
VREF Input port P3 Reference voltage input I/O port P2 I/O port P1 I/O port P0
Input port P5
I/O port P4
HARDWARE
Notes1 : 4096 bytes for M37471M2-XXXFP, and 8192 bytes for M37471M4/E4-XXXFP 2 : 128 bytes for M37471M2-XXXFP, and 192 bytes for M37471M4/E4-XXXFP
1.6 Functional block diagram
1-19
1-20
Reset input
RESET
M37477M8/E8-XXXSP/FP, M37477M8/E8TXXXSP/FP BLOCK DIAGRAM
Clock input XIN VCC
17 16
Clock output XOUT VSS Data bus
18
HARDWARE
14
15
Clock generating circuit (Note 2) RAM 384 bytes Timer 2(8) Control signal Processor status register PS(8) Index register X(8) Timer 3(8) Timer 4(8) PWM control Index register Y(8) Stack pointer S(8) Program counter PCH(8) Program counter PCL(8) 16384 bytes Timer 1(8) Instruction decoder ROM Instruction register(8) (Note 1)
1.6 Functional block diagram
8-bit Arithmetic and logical unit
Accumulator A(8)
INT1 A-D converter CNTR1 4 P3(4) P2(4) CNTR0 INT0
Fig. 1.6.4 M37477MX/E8-XXXSP/FP, M37477MX/E8TXXXSP/FP functional block diagram
7470/7471/7477/7478 GROUP USER'S MANUAL
Serial I/O(8) P1(8)
22 21 20 19 13 9 10 11 12 1 2 3 4 5 6 7 8
P4(2)
P0(8)
24 23
32 31 30 29 28 27 26 25
VREF Input port P3 Reference voltage input Input port P2 I/O port P1 I/O port P0
I/O port P4
Notes 1 : 4096 bytes for M37477M2TXXXSP/FP, and 8192 bytes for M37477M4-XXXSP/FP and M37477M4TXXXSP/FP 2 : 128 bytes for M37477M2TXXXSP/FP, and 192 bytes for M37477M4-XXXSP/FP and M37477M4TXXXSP/FP
M37478M8/E8-XXXSP, M37478M8/E8TXXXSP, M37478E8SS BLOCK DIAGRAM
Clock input XIN Reset input
RESET
Clock output XOUT VCC
22 21
VSS
19
20 25
Clock generating circuit (Note 2) RAM 384 bytes Timer 2(8) Control signal Processor status register PS(8) Index register X(8) Timer 3(8) Timer 4(8) PWM control Index register Y(8) Stack pointer S(8) Program counter PCH(8) Program counter PCL(8) 16384 bytes Timer 1(8) Instruction decoder ROM Instruction register(8) (Note 1)
XCIN
XCOUT
8-bit Arithmetic and logical unit
Accumulator A(8)
XCOUT A-D converter CNTR1 8 P3(4) P2(8) CNTR0 INT0
INT1
Fig. 1.6.5 M37478MX/E8-XXXSP, M37478MX/E8TXXXSP, M37478E8SS functional block diagram
Serial I/O(8)
7470/7471/7477/7478 GROUP USER'S MANUAL
P1(8)
29 28 27 26 18 10 11 12 13 14 15 16 17 2 3 4 5 6 7 8 9
XCIN
P5(4)
P4(4)
P0(8)
1 42 24 23
33 32 31 30
41 40 39 38 37 36 35 34
VREF Input port P3 Reference voltage input Input port P2 I/O port P1 I/O port P0
Input port P5
I/O port P4
HARDWARE
Notes 1 : 4096 bytes for M37478M2TXXXSP, and 8192 bytes for M37478M4-XXXSP and M37478M4TXXXSP 2 : 128 bytes for M37478M2TXXXSP, and 192 bytes for M37478M4-XXXSP and M37478M4TXXXSP
1.6 Functional block diagram
1-21
1-22
Reset input
RESET
M37478M8/E8-XXXFP, M37478M8/E8TXXXFP BLOCK DIAGRAM
Clock input XIN VCC
23 22 51 21
Clock output XOUT VSS AVSS Data bus
28
HARDWARE
18
19
Clock generating circuit (Note 2) RAM ROM 16384 bytes Timer 2(8) Control signal Processor status register PS(8) Index register X(8) Index register Y(8) Timer 3(8) Timer 4(8) PWM control Stack pointer S(8) Timer 1(8) Instruction decoder 384 bytes Program counter PCH(8) Program counter PCL(8) Instruction register(8) (Note 1)
1.6 Functional block diagram
XCIN
XCOUT
8-bit Arithmetic and logical unit
Accumulator A(8)
XCOUT A-D converter CNTR1 8 P3(4) P2(8) CNTR0 INT0
INT1
Fig. 1.6.6 M37478MX/E8-XXXFP, M37478MX/E8TXXXFP functional block diagram
7470/7471/7477/7478 GROUP USER'S MANUAL
Serial I/O(8) P1(8)
33 32 31 30 15 7 8 9 10 11 12 13 14 53 54 55 2 3 4 5 6
XCIN
P5(4)
P4(4)
P0(8)
52 49 26 25
38 37 36 35
48 47 46 43 42 41 40 39
VREF Input port P3 Reference voltage input Input port P2 I/O port P1 I/O port P0
Input port P5
I/O port P4
Notes 1 : 4096 bytes for M37478M2TXXXFP, and 8192 bytes for M37478M4-XXXFP and M37478M4TXXXFP 2 : 128 bytes for M37478M2TXXXFP, and 192 bytes for M37478M4-XXXFP and M37478M4TXXXFP
HARDWARE
1.7 Central processing unit (CPU)
1.7 Central processing unit (CPU)
The CPU of 7470/7471/7477/7478 group has the following 6 registers (referred as "CPU registers"). q q q q q q Accumulator (A) ********************************************************** 8-bit Index register X (X) *************************************************** 8-bit Index register Y (Y) *************************************************** 8-bit Stack pointer (S) ******************************************************** 8-bit Processor status register (PS) ********************************* 8-bit Program counter (PC) ********************************************** 16-bit
high-order (PCH) ********** 8-bit low-order (PCL) ************ 8-bit
Figure 1.7.1 shows a structure of CPU registers.
7
0
A
7 0
Accumulator
X
7 0
Index Register X
Y
7 0
Index Register Y
S
15 87 0
Stack Pointer
PCH
7
PCL
0
Program Counter
NVTBD I Z C
Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag
Fig. 1.7.1 Structure of CPU registers
7470/7471/7477/7478 GROUP USER'S MANUAL
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HARDWARE
1.7 Central processing unit (CPU)
The CPU register states provided immediately after hardware reset are described below. q The interrupt disable flag (I) of the Processor status register (PS) is set to "1." q The high-order 8 bits (PCH) of the Program counter (PC) become the contents of address FFFF16 and the low-order 8 bits (PCL) become the contents of address FFFE16. The contents of the other CPU registers are undefined, so be sure to initialize the CPU registers with the program. 1.7.1 Accumulator (A) The Accumulator is the central of microcomputer and is an 8-bit register. This accumulator is used for arithmetic operations, data transfer, temporary storage, condition judgment, and is a general-purpose register with the highest frequency of use. 1.7.2 Index register X (X), Index register Y (Y) The Index register X and the Index register Y are 8-bit registers. In the addressing mode using these Index registers, a value resulting from adding the contents of this register to the operand becomes a real specified address. This addressing mode is used to make reference to a subroutine table or a memory table. The Index registers are provided with increment, decrement, comparison and data transfer functions and can also be used as a simplified accumulator. In the Index register X, when the index X mode flag (T) of the Processor status register is "1," the contents of the Index register become an operand address. 1.7.3 Stack pointer (S) The Stack pointer is an 8-bit register which is used to call a subroutine or generate an interrupt. For a branch from a routine being executed to a subroutine or an interrupt processing routine, it is necessary to temporarily store (push) in memory the return address at the termination of this processing. Usually, the internal RAM is used as the push destination, and this area is called a stack area. The stack pointer indicates an address in the stack area to which the data will be pushed next. Figure 1.7.2 shows a push operation to the stack area of the register and a pop operation from the Stack area of the register. The Program counter and registers other than the Processor status register are not automatically pushed. Accordingly, be sure to push necessary registers with the program. The PHA instruction and the PLA instruction are used for push and pop operations of the Accumulator and the PHP instruction and the PLP instruction are used for push and pop operations of the Processor status register. In the 7470/7471/7477/7478 group, the RAM in 0 page or 1 page is available as a stack area. Select it by the stack page bit (bit 2) of the CPU mode register (address 00FB16), which will be described later ("0" for 0 page or "1" for 1 page). In some products whose RAM capacity is 192 bytes or less, RAM does not exist on 1 page, so be sure to set this bit to "0." The stack pointer is in an undefined state immediately after hardware reset. Be sure to initialize so as not to destroy the data arranged in the RAM area.
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7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
1.7 Central processing unit (CPU)
On-going routine
****** When an interrupt is accepted Interrupt request (Note) M(S) (S) ****** M(S) (S) When a subroutine is called Execute JSR M(S) (S) (PCH) (S)-1 (PCL) (S)-1 (PS) (S)-1
Push contents of Processor status register on stack Push return address on stack
M(S)
Push return address on stack
(PCH) (S)-1 (PCL) (S)-1 ******
Interrupt Service Routine * * * Execute RTI
(S) M(S) (S)
I Flag is set from "0" to "1" Fetch the Jump Vector
Subroutine (S) * * * Execute RTS (S)
Pop return address from stack
(S)+1 M(S) (S)+1 M(S) (S)+1 M(S)
(PS) (S) (PCL) (S)
Pop contents of Processor status register from stack
Pop return address from stack
(S)+1 M(S) (S)+1 M(S)
(PCH)
(PCL) (S) (PCH)
: Operation instructed by software : Operation which is automatically performed by hardware
Note : Condition for acceptance of an interrupt * * *
Interrupt disable flag is "0" (enable state) Interrupt enable bit is "1" (enable state)
Fig. 1.7.2 Register push and pop at interrupt generation and subroutine call
7470/7471/7477/7478 GROUP USER'S MANUAL
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HARDWARE
1.7 Central processing unit (CPU)
1.7.4 Program counter (PC) The Program counter is a 16-bit counter consisting of an 8-bit register PCH and an 8-bit register PCL. This counter indicates the address at which the next instruction to be executed is stored. The contents of this counter are automatically pushed to the stack when a subroutine is called or an interrupt occurs. The high-order 8 bits (PCH) of the program counter become the contents of address FFFF16 and the loworder 8 bits (PCL) become the contents of address FFFE16 immediately after hardware reset. 1.7.5 Processor status register (PS) The Processor status register is an 8-bit register consisting of 5 flags to indicate the state immediately after arithmetic processing and 3 flags to determine an operation for the CPU. Each bit of the Processor status register is described below. (1) Carry flag (C) ...................................................... Bit 0 The carry flag holds the carry or borrow from the arithmetic logical unit after arithmetic processing. This flag is also changed by the Shift instruction or Rotate instruction. This flag is set to "1" by the SEC instruction and cleared to "0" by the CLC instruction. (2) Zero flag (Z) ........................................................ Bit 1 The zero flag is set to "1" when the arithmetic processing or data transfer result is "0" and cleared to "0" in all other cases. In the decimal operation mode, this flag is invalidated. There is no instruction to change the contents of this flag. (3) Interrupt disable flag (I) ................................... Bit 2 The interrupt request flag disables all instructions (except an interrupt by the BRK instruction). When this flag is "1," the interrupt disable state is provided. This flag is set to "1" by accepting an interrupt, thereby disabling a multi-interrupt. This flag is set to "1" by the SEI instruction and cleared to "0" by the CLI instruction. This flag is set to "1" (interrupt disable state) immediately after hardware reset. (4) Decimal mode flag (D) ...................................... Bit 3 The decimal mode flag determines whether addition and subtraction should be performed in binary or decimal notation. When the contents of this flag are "0," an ordinary binary operation is performed. When they are "1," an arithmetic operation is performed assuming that one word is a 2-digit decimal number. In a decimal operation, decimal compensation is automatically performed (decimal operation can be performed only by the ADC instruction and the SBC instruction). This flag is set to "1" by the SED instruction and cleared to "0" by the CLD instruction. This flag is put in an undefined state immediately after hardware reset. As this flag directly affects arithmetic operations, be sure to initialize it. (5) Break flag (B) ...................................................... Bit 4 The break flag identifies whether or not an interrupt has been caused by the BRK instruction. The BRK instruction is used for program debugging and performs the same operation as an interrupt is performed by executing the BRK instruction. The Processor status register is pushed to the stack, after the B flag is automatically set to "1" in case of the BRK instruction interrupt, or after the B flag is automatically cleared to "0" in case of the other interrupts. There is no instruction to change the contents of this flag.
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7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
1.7 Central processing unit (CPU)
(6) Index X mode flag (T) ....................................... Bit 5 When the Index X mode flag is "0," arithmetic operations are performed between the Accumulator and the memory. When this flag is "1," direct arithmetic operations and direct data transfer between one memory and another, between a memory and an I/O, or between one I/O and another without passing through the accumulator. An arithmetic operation result between memory 1 directly specified by the Index register X and memory 2 specified by an operand is stored into memory 1. 1 When the T flag is "0" A A V M2 2 When the T flag is "1" M1 M1 V M2 V : Denotes an arithmetic operation A : Content of accumulataor M1 : Contents of memory 1 directly specified by the Index register X M2 : Contents of memory 2 specified by the operand

This flag is set to "1" by the SET instruction and cleared to "0" by the CLT instruction. This flag is in the undefined state immediately after hardware resetting. This flag has a direct effect on arithmetic operations. Accordingly, be sure to initialize it. (7) Overflow flag (V) ................................................ Bit 6 The contents of the overflow flag have significance when addition and subtraction are performed assuming that one word is a signed binary number. When an addition or subtraction result exceeds the range of +127 to -128, this flag is set to "1." When the BIT instruction is executed for other cases, the contents of bit 6 of the executed memory are put into the overflow flag. This flag is cleared to "0" by the CLV instruction, but there is no instruction to set this flag to "1." In the decimal operation mode, this flag is invalidated. (8) Negative flag (N) ................................................ Bit 7 The negative flag is set to "1" when an arithmetic processing or data transfer result is negative (bit 7 is "1"). The contents of bit 7 of the executed memory are put into this flag when the BIT instruction is executed. There is no instruction to change the contents of this flag. In the decimal operation mode, this flag is invalidated.
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1.8 Access area
1.8 Access area
In the 7470/7471/7477/7478 group, all ROM, RAM and I/O and the various control registers are located in the same memory area. Accordingly, the same instructions are used for data transfer and arithmetic operations without discriminating between a memory and an I/O. The Program counter consists of 16 bits and the access space is 64K-byte of memory area: addresses 000016 to FFFF16. The area of the least significant 256 bytes (addresses 000016 to 00FF16) is called the "zero page," and memories with a high frequency of use such as internal RAM, I/O ports and timers are located here. The area of the most significant 256 bytes (addresses FF0016 to FFFF16) is called the "special page," and an internal ROM and interrupt vectors are located here. The zero page and the special page can be accessed with 2 bytes by using each special addressing mode. Figure 1.8.1 shows an outline of accsess area.
000016
RAM
00C016 00FF16
Zero page
SFR area
RAM
FF0016
ROM
Special page
FFFF16
Interrupt vector area
Fig. 1.8.1 Access area
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1.8 Access area
1.8.1 Zero page (Addresses 000016 to 00FF16) The area of 256 bytes from addresses 000016 to 00FF16 is called the zero page. The internal RAM and the special function register (SFR) are located in this area. To specify a memory or a register in this area, use the addressing mode shown in Table 1.8.1. In this area, especially, it is possible to access this area in a shorter instruction cycle by using the zero addressing mode. 1.8.2 Special page (Addresses FF0016 to FFFF16) The area of 256 bytes from addresses FF0016 to FFFF16 is called the special page. The internal ROM and the interrupt vector area are located in this area. To specify a memory or subroutine in this area, use the addressing mode shown in Table 1.8.1. In this area, especially, it is possible to jump to this area in a shorter instruction cycle by using the special page addressing mode. Ordinary, subroutines with high frequency of use are located in this area. Table 1.8.1 Addressing mode accessible to each area Addressing mode (bytes required) Zero page (2) Zero page indirect (2) Zero page X (2) Zero page Y (2) Zero page bit (2) Zero page bit relative (3) Absolute (3) Absolute X (3) Absolute Y (3) Relative (2) Indirect (3) Indirect X (2) Indirect Y (2) Special page (2) Zero page reference , , , , , , , , , , , , , -- Special page reference -- -- -- -- -- -- , , , , , , , , Other area reference -- -- -- -- -- -- , , , , , , , --
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1.9 Memory allocation
1.9 Memory allocation
Figure 1.9.1 and Figure 1.9.2 show the memory allocation of 7470/7471/7477/7478 group. The memories, I/Os and others located in the access area are explained below. q RAM An internal RAM is located in each area shown in Table 1.9.1. The internal RAM is used as a data storage area and a stack area for subroutine call and interrupt occurrence. When the RAM is used as a stack area, be careful about subroutine nesting depth and interrupt levels so that the data in the RAM is not destroyed. q Special function register (SFR) (Addresses 00C016 to 00FF16) The area from addresses 00C016 to 00FF16 is assigned to the SFR (Special Function Register). Various control registers such as I/O ports, timers, serial I/Os, A-D converters and interrupts are located in this SFR. Figure 1.9.3 shows the special function register (SFR)memory map. q ROM An internal ROM is located in each area shown in Table 1.9.2. The internal ROM is used to store data tables and programs. In the internal ROM, a vector area to store jump destination addresses upon a reset or occurrence of interrupt are assigned to addresses FFEA16 to FFFF16 in the 7470/7471 group and to addresses FFE816 to FFFF16 in the 7477/7478 group. Figure 1.9.4 shows the interrupt vector memory map. Table 1.9.1 RAM area Product Range M3747xM2 Addresses 000016 to 007F16 M3747xM4/E4 Addresses 000016 to 00BF16 M3747xM8/E8 Addresses 000016 to 00BF16, Addresses 010016 to 01BF16 Table 1.9.2 ROM area Product Memory type M3747xM2 Mask ROM M3747xM4 Mask ROM M3747xE4 Programmable ROM M3747xM8 Mask ROM M3747xE8 Programmable ROM
Memory size 128 ! 8-bit 192 ! 8-bit 384 ! 8-bit
Range Addresses F00016 to FFFF16 Addresses E00016 to FFFF16 Addresses C00016 to FFFF16
Memory size 04K ! 8-bit 08K ! 8-bit 16K ! 8-bit
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1.9 Memory allocation
M37470M2 M37471M2
000016 007F16 00C016 00FF16 RAM (128 bytes) Not used SFR area 000016 007F16
M37470M4/E4 M37471M4/E4
RAM (192 bytes) 000016 007F16
M37470M8/E8 M37471M8/E8
RAM (192 bytes) Zero page SFR area RAM (192 bytes)
00C016 00FF16
SFR area
00C016 00FF16 010016
01BF16
Not used
Not used
Not used
C00016
E00016
F00016
ROM (4096 bytes)
ROM (8192 bytes) FF0016 FFEA16 Interrupt vector area FFFF16
ROM (16384 bytes) FF0016 FFEA16 Interrupt vector area FFFF16 Special page
FF0016 FFEA16 Interrupt vector area FFFF16
Fig. 1.9.1 Memory allocation of 7470/7471 group
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1.9 Memory allocation
M37477M2 M37478M2
000016 007F16 00C016 00FF16 RAM (128 bytes) Not used SFR area 00C016 00FF16 000016 007F16
M37477M4 M37478M4
RAM (192 bytes)
M37477M8/E8 M37478M8/E8
000016 007F16 00C016 00FF16 010016 RAM (192 bytes) Zero page SFR area RAM (192 bytes)
SFR area
01BF16
Not used
Not used
Not used
C00016
E00016
F00016
ROM (4096 bytes)
ROM (8192 bytes) FF0016 FFE816 Interrupt vector area FFFF16
ROM (16384 bytes) FF0016 FFE816 Interrupt vector area FFFF16 Special page
FF0016 FFE816 Interrupt vector area FFFF16
Fig. 1.9.2 Memory allocation of 7477/7478 group
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1.9 Memory allocation
00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16
Port P0 Port P0 direction register Port P1 Port P1 direction register Port P2 Port P2 direction register (Note 1) Port P3 Port P4 Port P4 direction register Port P5 (Note 2)
Port P0 pull-up control register
Port P1-P5 pull-up control register (Note 3)
Edge polarity selection register Input latch register
A-D control register A-D conversion register Serial I/O mode register Serial I/O register Serial I/O counter Byte counter
(Note 4)
00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16
Transmit/receive buffer register Serial I/O status register Serial I/O control register UART control register Baud rate generator
(Note 5)
Timer 1 Timer 2 Timer 3 Timer 4
Timer FF register Timer 12 mode register Timer 34 mode register Timer mode register 2 CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2
Notes 1: In the 7477/7478 group, this register is not located. 2: In the 7470/7477 group, this register is not located. 3: This address is allocated P1-P4 pull-up control register for the 7470/7477 group. 4: In the 7477/7478 group, this register is not located. 5: In the 7470/7471 group, this register is not located.
Fig. 1.9.3 Special function register (SFR) memory map
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1.9 Memory allocation
FFEA16 FFEB16 FFEC16 FFED16 FFEE16 FFEF16 FFF016 FFF116 FFF216 FFF316 FFF416 FFF516 FFF616 FFF716 FFF816 FFF916 FFFA16 FFFB16 FFFC16 FFFD16 FFFE16 FFFF16
BRK instruction interrupt
A-D conversion completion interrupt
Serial I/O interrupt Timer 4 interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt
CNTR0 interrupt or CNTR1 interrupt INT1 interrupt or key on wake up interrpt
INT0 interrupt RESET
FFE816 FFE916 FFEA16 FFEB16 FFEC16 FFED16 FFEE16 FFEF16 FFF016 FFF116 FFF216 FFF316 FFF416 FFF516 FFF616 FFF716 FFF816 FFF916 FFFA16 FFFB16 FFFC16 FFFD16 FFFE16 FFFF16
BRK instruction interrupt
A-D conversion completion interrupt
Serial I/O transmit interrupt Serial I/O receive interrupt Timer 4 interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt
CNTR0 interrupt or CNTR1 interrupt INT1 interrupt or key on wake up interrpt
INT0 interrupt RESET
7470/7471 group
7477/7478 group
Fig. 1.9.4 Interrupt vector memory map
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1.10 I/O pins
1.10 I/O pins
The 7470/7471/7477/7478 group is provided with the following I/O pins. q I/O port (P0 to P5) q Reset input (RESET) q Clock input/output (XIN, XOUT, XCIN, XCOUT) q A-D convesion reference voltage input (VREF) q Power supply voltage input (VCC, VSS, AVSS) Notes 1: The 7470/7477 group is not provided with port P5 and pins XCIN and XCOUT. 2: The AVSS pin is dedicated to the 56P6N-A package product. For an outline of each pin, refer to "1.5 Pin description." 1.10.1. I/O port (1) I/O port writing and reading 2 The input-only pin and the programmable I/O port set as input port The values (pin states) which input to the input-only pin and to the programmable I/O port set as input port can be read in by reading the Port register corresponding to each port. When data is written into the Port register corresponding to each port, it can be only written in the Port register and has no effect on the pin state. 2 The programmable I/O port set as an output port The value written into the Port register corresponding to the programmable I/O port set as an output port is output to the outside by way of a transistor. When the Port register corresponding to each port has been read, each pin state is not read in but the value written into the Port register is read. Accordingly, if the output "H" voltage has been reduced or the output "L" voltage has been increased by an external load, the previous output value can be correctly read. Figure 1.10.1 shows the I/O port writing and reading and Table 1.10.1 shows the port register address allocation.
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1.10 I/O pins
At input : A write operation is enabled to the Port register. Each pin state can be read in by reading the Port register.
At output : An output value can be set by writing to the Port register. The Port register can be read out.
Port direction register ( "0" )
"H" level output
*
Port direction register ( "1" )
Port register (When Writing) Port register
Port register (When Reading)
"L" level output
* : The P channel transistor and the N channel transistor are in a cut-off state.
Fig. 1.10.1 I/O port writing and reading
Table 1.10.1 Port register address allocation Port register Address P0 00C016 P1 00C216 P2 00C416 00C616 P3 00C816 P4 00CA16 P5 (Note) Note: The 7470/7477 group is not provided with P5.
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1.10 I/O pins
(2) Input/output selection of the programmable I/O ports An input/output selection of the programmable I/O ports is made by the Port direction register corresponding to each port. Figure 1.10.2 shows a structure of Port Pi (i = 0, 1, 2, 4) direction register. Note: Each direction register is initialized into "0016" at reset, so that the I/O ports are put into an input state.
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0,1,2,4) [Address 00C116, 00C316, 00C516, 00C916] B Name Function 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode
At reset
RW
0 Port Pi direction register 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
Notes 1: The 7477/7478 group is not provided with the port P2 direction register (input only). 2: The Port P4 is provided as below: *7470/7477 group has 2 bits of P4 0 and P41. *7471/7478 group has 4 bits of P4 0 to P43.
Fig. 1.10.2 Structure of Port Pi direction register (i=0, 1, 2, 4)
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1.10 I/O pins
(3) Pull-up control When input has been selected by the Port direction register, pull-up control can be exerted in bit units shown in Table 1.10.1 by the Port P0 pull-up control register (address 00D016) or the Port P1-P5 pull-up control register* (address 00D116). At this time, control is exerted by turning on and off the pull-up transistor. *: The Port P1-P4 pull-up control register is arranged in the 7470/7477 group. Note: Ports other than P0 cannot be controlled in one-bit units. For example, when P10 is pulled up at P1 (pull-up control in units of 4 bits), P11 to P13 are also pulled up. Figure 1.10.3 shows a structure of Port P0 pull-up control register, and Figure 1.10.4 shows a structure of Port P1-P5 pull-up control register.
Port P0 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 pull-up control register [Address 00D016] B 0 1 2 3 4 5 6 7 Name Port P00 pull-up control bit Port P01 pull-up control bit Port P02 pull-up control bit Port P03 pull-up control bit Port P04 pull-up control bit Port P05 pull-up control bit Port P06 pull-up control bit Port P07 pull-up control bit Function 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up
At reset
RW
0 0 0 0 0 0 0 0
Fig. 1.10.3 Structure of Port P0 pull-up control register
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1.10 I/O pins
Ports P1 to P5 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Ports P1 to P5 pull-up control register [Address 00D116] b 0 1 2 3 4 5 6 7 Name Ports P10 to P13 pull-up control bit Ports P14 to P17 pull-up control bit Ports P20 to P23 pull-up control bit (Note 2) Function
At reset
RW
0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up Ports P24 to P27 pull-up 0 : No pull-up control bit (Notes 2, 3) 1 : Pull-up Ports P40 to P43 pull-up 0 : No pull-up control bit (Note 4) 1 : Pull-up Nothing is allocated for this bit. This is write disabled bit and is undefined at reading. Ports P50 to P53 pull-up 0 : No pull-up control bit (Note 3) 1 : Pull-up Nothing is allocated for this bit. This is write disabled bit and is undefined at reading.
0 0 0 0 0 ? 0 ? ?! ?!
Notes 1 : In the 7470/7477 group, the P1 to P4 Pull-up control register is provided. 2 : In the 7477/7478 group, nothing is allocated to these bits. They are undefined at reading. 3 : In the 7470/7477 group, nothing is allocated to these bits. They are undefined at reading. 4 : The 7470/7477 group is provided with only P40 and P41.
Fig. 1.10.4 Structure of Ports P1 to P5 pull-up control register
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1.10 I/O pins
1.10.2 Port block diagram Figure 1.10.5 to Figure 1.10.9 show the block diagram of I/O ports.
Port P0
Pull-up control register
Tr1
Direction register
Data bus
Port latch
Port P0
Port P1
Data bus
Interrupt control circuit
Pull-up control register
T34M7 Tr2
Direction register
Data bus
Port latch
Port P13
T1 T12M3 Tr3
Direction register
Data bus
Port latch
Port P12
T0 Tr4
Direction register
Data bus
Port latch
Port P11
Tr5
Direction register
Data bus
Port latch
Port P10
Tr1-Tr5 are pull-up transistors
Fig. 1.10.5 Block diagram of Ports P0, P10 to P13
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1.10 I/O pins
Port P14-P17
Direction register
Data bus
SM7 SM4 Tr6
Port latch
Port P17
SRDY
SM2 SM3
Tr7
Direction register
Data bus
Port latch
Port P16
CLK output
CLK input
SM3
Tr8 SM7
Direction register
Data bus
Port latch
Port P15
SOUT Tr9
Direction register
Data bus
Port latch
Port P14
SIN Data bus
Pull-up control register
Tr6-Tr9 are pull-up transistors
Fig. 1.10.6 Block diagram of Ports P14 to P17 (7470/7471 group)
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1.10 I/O pins
Port P14-P17
SIOE SIOM SRDY
Tr6
Direction register
Data bus
Port latch
Port P17
SRDY SCS SIOE SIOM SIOE
Tr7
Direction register
Data bus
Port latch
Port P16
SCLK output SIOE TE
SCLK input
Tr8
Direction register
Data bus
Port latch
Port P15
TXD SIOE RE
Tr9
Direction register
Data bus
Port latch
Port P14
RXD Data bus
Pull-up control register
Tr6-Tr9 are pull-up transistors
Fig. 1.10.7 Block diagram of Ports P14 to P17 (7477/7478 group)
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1.10 I/O pins
Port P2 (7470/7471 group)
* : Control in units of 4-bit
Data bus Pull-up control register
*
Tr10
Direction register Data bus Port latch Port P2
A-D conversion circuit
Multiplexer
Port P2 (7477/7478 group)
Data bus Port P2
A-D conversion circuit
Multiplexer
Port P3
Data bus Port P3
INT0, INT1 CNTR0, CNTR1
Port P4
Data bus Pull-up control register
* : Control in units of 4-bit (Control in units of 2-bit for 7470/7477 group)
*
Tr11 (7470/7471 group) Tr10 (7477/7478 group)
Port P4
Direction register Data bus Port latch
Tr10 and Tr11 are pull-up transistors
Fig. 1.10.8 Block diagram of Ports P2 to P4
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1.10 I/O pins
Port P5 (7471/7478 group)
Pull-up control register
Tr12 (7471 group) Tr11 (7478 group) Data bus Port P53
Data bus
Tr13 (7471 group) Tr12 (7478 group) Data bus Port P52
CM4
Tr14 (7471 group) Tr13 (7478 group)
Data bus Port P51
CM4
CM4
XCIN
CM4
Tr15 (7471 group) Tr14 (7478 group)
Data bus Port P50
Tr11-Tr15 are pull-up transistors
Fig. 1.10.9 Block diagram of Port P5
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1.10 I/O pins
1.10.3 Notes on use When using I/O ports, note the following. (1) Modify of the content of I/O port latch When the content of the port latch of an I/O port is modified with the bit managing instruction*, the value of the unspecified bit may be changed. Reason The bit managing instruction is read-modify-write instruction for reading and writing data by a byte unit. Accordingly, when this instruction is executed on one bit of the port latch of an I/O port, the following is executed to all bits of the port latch. q As for a bit which is set as an input port: The pin state is read in the CPU, and is written to this bit after bit managing. q As for a bit which is set as an output port: The bit value is read in the CPU, and is written to this bit after bit managing. Make sure the following: q Even when a port which is set as an output port is changed for an input port, its port latch holds the output data. q Even when a bit of a port latch which is set as an input port is not specified with a bit managing instruction, its value may be changed in case where content of the pin differs from a content of the port latch. bit managing instructions: SEB and CLB instruction (2) Pull-up control To pull-up ports by software, note the following. q When P1 is used in the serial I/O mode, the pull-up settings corresponding to P14 to P17 are invalidated (pull-up is impossible). Refer to the port block diagram for details. q When a port is set in the output mode, the pull-up setting corresponding to the port is invalidated (pull-up is impossible). q Ports other than P0 cannot be controlled in one-bit units. For example, when P10 is pulled up at P1 (pull-up control in units of 4 bits), P11 to P13 are also pulled up.
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1.10 I/O pins
(3) Fix of a port input level in stand-by state Fix input levels of an input and an I/O port for getting effect of low-power dissipation in stand-by state , especially for the I/O ports of the N-channel open-drain. Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor. When determining a resistance value, make sure the following: q External circuit q Variation of output levels during the ordinary operation : "Stand-by state": The stop mode by execution of the STP instruction or the wait mode by execution of the WIT instruction: Reason Even when setting as an output port with its direction register, in the following state: * N-channel ....... when the content of the port latch is "1" the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Make sure that the level becomes "undefined" depending on external circuits. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input and an I/O port are "undefined." This may cause power source current.
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1.10 I/O pins
(4) Termination of unused pins Table 1.10.2 shows a termination of unused pins. Table 1.10.2 Termination of unused pins Terminations Pull-up (connect to VCC) Pull down (connect to Connect Connect Open to to ports through a resistor VSS) ports through a (Note 1) resistor (Note 2) VCC VSS (Note 2) , (Note 4) , (Note 4) , (Note 6) , (Note 6) , (Note 5)
Port P0 P10 to P13 P15, P17 P2 (7470/7471 group) P4 P14, P16
,
x
x
, x x (Note 5) , , , P2 (7477/7478 group) x (Note 6) (Note 6) (Note 6) , , , P30 to P33 x (Note 6) (Note 6) (Note 6) , P5 x x , , (Note 8) (Note 7) x VREF , x x x x AVSS x , x x Notes 1: A pin that can be opened at the unused time has a circuit that does not allow a current to flow into itself unless any read signal is internally input even if a medium-level input is applied at the open state. 2: For programmable I/O ports, do not connect two or more ports together through a resistor to VCC or VSS. 3: Note the following when setting them to the output mode and making the pins open. * The ports function as input ports in the period from reset release till switching the ports to the output mode by software. Accordingly, the power source current may be increased depending on the input levels of the pins. * If the Port direction register has been changed into the input mode by runaway or noise, re-set the Port direction register to the output mode periodically by software. 4: To pull up a pin, set the Port direction register and the Port latch so that this pin may be into the input mode or "H" output state. 5: To pull down a pin, set the Port direction register, the Port pull-up control register and the Port latch so that this pin may be put in the no pull-up transistor state in the input mode or in the "L" output state. 6: These pins are connect to the VCC or VSS without a resistor when the wiring is the shortest. However, they are connect to the VCC or VSS through a resistor. In addition, the P33 pin of the built-in programmable ROM version is used in common with the VPP pin, insert a resistor of about 5 k in series and connect by the shortest wiring. 7: When using neither the P50 pin nor the P51 pin (used in common with the XCIN and XCOUT pin), set bit 4 of the CPU mode register to "0" (P50 and P51 functions). 8: To pull down a pin, set the port pull-up control register so that a pull-up transistor will not be provided for this pin.
, (Note 3)
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1.11 Interrupts
1.11 Interrupts
Interrupts are used in the following cases. q When it is requested to execute higher-priority processing than the processing routine being executed. q When it is necessary to observe any timing for processing. The 7470/7471 group can generate interrupts from 12 sources and the 7477/7478 group can generate interrupts from 13 sources. 1.11.1 Description of interrupt source 2 Priority of interrupt The interrupts are vector interrupts with a fixed priority sequence. When two or more interrupt requests occur at the same sampling time, they are accepted starting with the highest-priority interrupt. This priority is determined by hardware. However, a variety of priority processing can be executed by software when the interrupt control flags (interrupt enable bit and interrupt disable flag) are used. 2 Acceptance of interrupt The corresponding interrupt request bit is set to "1" upon occurrence of an interrupt. When the following conditions are satisfied in this state, this interrupt is accepted. For the details, refer to "1.11.3 Interrupt control." 1 When the interrupt disable flag is cleared to "0" (interrupt enable state) 2 When the interrupt enable bit is set to "1" (interrupt enable state) Table 1.11.1 shows an interrupt priority, interrupt sources and vector addresses. Table 1.11.1 Interrupt sources and priority Vector Interrupt source Priority 7470/7471 group 7477/7478 group High 1 Reset (Note) FFFF16 2 INT0 interrupt FFFD16 3 INT1 interrupt or key-on wake up interrupt FFFB16 4 CNTR0 interrupt or CNTR1 interrupt FFF916 5 Timer 1 interrupt FFF716 6 Timer 2 interrupt FFF516 7 Timer 3 interrupt FFF316 8 Timer 4 interrupt FFF116 Serial I/O interrupt Serial I/O receive interrupt FFEF16 9 10 A-D conversion completion interrupt Serial I/O transmit interrupt FFED16 A-D conversion 11 BRK instruction interrupt FFEB16 completion interrupt BRK instruction interrupt FFE916 12 Note: A reset operation is performed in the same way as
address Lower FFFE16 FFFC16 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16
Remark Non-maskable Polarity programmable INT1: polarity programmable Polarity programmable
FFE816 an interrupt, so it is described in the table.
BRK instruction interrupt is nonmaskable software interrupt
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(1) INT interrupt When detecting a rising edge or a falling edge of each INT pin (INT0, INT1), the microcomputer generates an INT interrupt request.These polarity is selected by the edge polarity selection register (EG: Address 00D416). 2 P30, P31 pins The INT0 and INT1 pins are used in common with the P30 and P31 pins and always detect the levels of P30 and P31. 2 In the stop mode/wait mode When bit 5 of the Edge polarity selection register is "0," a restoration can be attained by the INT interrupt from the stop mode/wait mode state provided by the STP/WIT instruction. For the details, refer to "1.17 Low-power dissipation function." 2 After reset At reset release, the Edge polarity selection register is cleared to "0016," so the INT0 and INT1 interrupts generate the interrupt request by detecting a falling edge. At reset release, however, the Interrupt control register is put into the interrupt disable state, so any interrupt is not accepted. Note: The INT0 and INT1 pins are used in common with input port P30 and P31, however, there is no register for switching between the INT pins and the ports, so the active edges of P30 and P31 are always detected. When these pins are used as ports, put the corresponding INT interrupt into the disable state. In the INT interrupt enable state, the INT interrupt is generated by a pin level change, thereby causing a program run away. (2) Key-on wake up interrupt When bit 5 of the Edge polarity selection register is "1," the key-on wake up interrupt request is generated by applying the "L" level to any pin of P0 being an input port in the stop mode/wait mode provided by the STP/WIT instruction, so that a recovery can be attained from the stop mode/wait mode. 2 After reset At reset release, bit 5 of the Edge polarity selection register is cleared to "0" so that the key-on wake up interrupt request does not occur in the stop mode/wait mode. Notes 1: In modes other than the stop mode/wait mode, the key-on wake up interrupt is disabled. 2: To select the stop mode/wait mode by the STP/WIT instruction when the interrupt disable flag is cleared to "0" and bit 5 of the Edge polarity selection register is set to "1," set every input to P0 to "H."
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Figure 1.11.1 shows a block diagram of interrupt input and key-on wake up circuit.
P33/CNTR1 Port P33 data read circuit EG3 P32/CNTR0 EG2 Port P32 data read circuit XCIN 1/2 P30/INT0 XIN 1/2 CM7 Port P30 data read circuit EG0 P31/INT1 Port P31 data read circuit EG1
Noise elimination circuit Noise elimination circuit
CNTR interrupt request signal EG4
INT0 interrupt request signal
EG5
INT1 interrupt request signal
CPU stop state signal Pull-up control register
P07
Direction register
P01
Pull-up control register Direction register
Port P0 data read circuit
Pull-up control register Direction register
P00
Note: The 7470/7477 group is not provided with the XCIN pin.
Fig. 1.11.1 Block diagram of interrupt input and key-on wake up circuit
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(3) CNTR interrupt When detecting a rising edge or a falling edge of each CNTR pin (CNTR0, CNTR1), the microcomputer generates an CNTR interrupt. For selecting the active edge of interrupt and the CNTR0/CNTR1 pin, the Edge polarity selection register (EG) is used. 2 After reset At reset release, the Edge polarity selection register is cleared to "0016," so the CNTR0 interrupts generate the interrupt request by detecting a falling edge. At reset release, however, the Interrupt control register is put into the interrupt disable state, so any interrupt is not accepted. Note: The CNTR0 and CNTR1 pins are used in common with input port P32 and P33, however there is no register for switching between the CNTR pins and the ports, so the active edges of P32 and P33 are always detected. When these pins are used as ports, put the corresponding CNTR interrupt into the disable state. In the CNTR interrupt enable state, the CNTR interrupt is generated by a pin level change, thereby causing a program run away. (4) Timer interrupt The microcomputer generates the interrupt request at the rise of the next count source after the respective timer overflows. For the details of the timer interrupt, refer to "1.12 Timers." (5) Serial I/O interrupt There is a difference in the serial I/O interrupt between the 7470/7471 group and the 7477/7478 group. 2 Serial I/O interrupt of 7470/7471 group An interrupt request is generated upon termination of the serial I/O transmit/receive. 2 Serial I/O interrupt of 7477/7478 group The serial I/O transmit interrupt and the serial I/O receive interrupt are available. q Serial I/O transmit interrupt For the Serial I/O transmit interrupt, interrupt request generation timing can be selected by bit 3 of the Serial I/O control register (SIOCON: Address 00E216) as shown below. 0: The data written in the Transmit buffer is transferred to the Transmit shift register, and when the Transmit buffer becomes empty, the interrupt request is generated. 1: The interrupt request is generated when a shift operation of the Transmit shift register terminates. Note: When the transmit enable bit is set to the enable state, the Transmit buffer becomes empty and the transmit shift terminates. Accordingly, the interrupt request can be generated by selecting one of these sources. To use the transmit interrupt, set the transmit enable bit to "1," clear the transmit interrupt request bit to "0," and then set the transmit interrupt enable bit to the enable state. q Serial I/O receive interrupt When all data has been put in the Receive shift register and the contents of the shift register have been transferred to the Receive buffer, the interrupt request is generated. For the details of the serial I/O interrupt, refer to "1.13 Serial I/O." (6) A-D conversion completion interrupt As soon as A-D conversion terminates, the interrupt request is generated. For the details of the A-D conversion completion interrupt, refer to "1.14 A-D Converter." (7) BRK instruction interrupt This is the lowest-priority software interrupt without any corresponding interrupt enable flag, and not affected by the interrupt disable flag. (Non maskable) For the details, refer to "SERIES 740 SOFTWARE USER'S MANUAL."
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1.11.2 Operation description (1) Interrupt operation After an interrupt is accepted, the contents of the register shown below are automatically pushed to the stack area in sequence in the order of 1, 2 and 3. 1 Program counter high-order (PCH) 2 Program counter low-order (PCL) 3 Processor status register (PS) After the above register is pushed, a branch is made to the vector address of the accepted interrupt. When the RTI instruction is executed at the end of the interrupt processing routine, the contents of the above register which were pushed onto the stack area are popped to the respective registers in sequence in the order of 3, 2 and 1, and the processing precedent to the acceptance of the interrupt is restarted. Figure 1.11.2 shows the interrupt operation.
Executing routine ******* Interrupt occurs (Accepting interrupt request)
Suspended Contents of Program counter (high-order) are pushed onto stack operation
Contents of Program counter (low-order) are pushed onto stack
Resume processing *******
Contents of Processor status register are pushed onto stack
Interrupt processing routine RTI instruction
Contents of Processor status register are popped from stack Contents of Program counter (low-order) are popped from stack Contents of Program counter (high-order) are popped from stack
: Operation commanded by software : Internal operation to be performed automatically
Fig. 1.11.2 Interrupt operation
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(2) Processing upon acceptance of interrupt When an interrupt is accepted, the following operations are automatically performed. 1 The processing being executed is interrupted. 2 The contents of the Program counter and the Processor status register are pushed to the stack area. Figure 1.11.3 shows a change of the contents of the Program counter and the Stack pointer upon acceptance of the interrupt. 3 The vector address (start address of the interrupt processing routine) stored in the vector area corresponding to the generated interrupt concurrently with pushing is set in the Program counter and the interrupt processing routine is executed. 4 After the interrupt processing routine is started, the corresponding interrupt request bit is automatically cleared to "0." The interrupt disable flag is set to "1," thereby disabling a multi-interrupt. To execute the interrupt processing routine, it is necessary to set a vector address in the vector area corresponding to each interrupt beforehand.
Program counter
PCL Program counter (low-order)
Stack area
PCH Program counter (high-order) Interrupt disable flag = "0"
Stack pointer
(S) S
(S)
Interrupt request is accepted
Program counter
PCL PCH Vector address (from Interrupt vector area) Interrupt disable flag = "1"
Stack area
(S) - 3 Processor status register Program counter (low-order)
Stack pointer
S (S) - 3
(S) Program counter (high-order)
Fig. 1.11.3 Changes of contents of Program counter and Stack pointer upon acceptance of interrupt
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(3) Timing after acceptance of interrupt The interrupt processing routine starts with the machine cycle after termination of the instruction being executed. Figure 1.11.4 shows a processing time up to the execution of the interrupt processing routine and Figure 1.11.5 shows a timing after acceptance of the interrupt.
Interrupt request occurs
Interrupt operation starts
Main routine
Waiting time for pipeline postprocessing
Push onto stack Vector fetch
Interrupt processing routine
0 to 16 cycles
2 cycles
5 cycles
7 to 23 cycles (At internal system clock = 4 MHz, 1.75 s to 5.75 s)
: At the DIV instruction executed.
Fig. 1.11.4 Processing time up to the execution of interrupt processing routine
Waiting time for pipeline postprocessing
Push onto stack Vector fetch
Interrupt operation starts
SYNC R/W Address bus Data bus
S, SPS S-1, SPS S-2, SPS BL BH AL, AH
PC
Not used
PCH
PCL
PS
AL
AH
SYNC : CPU operation code fetch cycle (This is an internal signal which cannot be observed from the external unit.) BL, BH : Vector address of each interrupt AL, AH : Jump destination address of each interrupt SPS : "0016" or "0116" (when the stack page bit is "0," SPS is 0016," and when the bit is "1," SPS is "0116")
Fig. 1.11.5 Timing after acceptance of interrupt
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1.11.3 Interrupt control Regarding interrupts other than the BRK instruction, the acceptance of them can be controlled by the interrupt request bit, the interrupt enable bit and the interrupt disable flag. This section describes interrupt control other than the BRK instruction. Figure 1.11.6 shows a interrupt control diagram.
Interrupt request bit Interrupt enable bit Interrupt accepted Interrupt disable flag BRK instruction Reset
Fig. 1.11.6 Interrupt control diagram The interrupt request bit, the interrupt enable bit and the interrupt disable flag function independently and do not affect one another. An interrupt is accepted when all the following conditions are satisfied. q Interrupt request bit ............. "1" q Interrupt enable bit .............. "1" q Interrupt disable flag ............ "0" The priority is determined by hardware. However, a variety of priority processing can be executed by software when the above flag and bits are used. Table 1.11.2 shows a interrupt control bits for individual interrupt sources. Table 1.11.2 Interrupt control bits for individual interrupt sources Interrupt request bits Interrupt source Address Bits 00FC16 b0 Timer 1 00FC16 b1 Timer 2 00FC16 b2 Timer 3 00FC16 b3 Timer 4 00FC16 b6 (Note 1) Serial I/O (7470/7471 group) 00FC16 b5 (Note 2) Serial I/O receive (7477/7478 group) 00FC16 b6 (Note 2) Serial I/O transmit (7477/7478 group) 00FC16 b7 A-D conversion 00FD16 b0 INT0 00FD16 b1 INT1 00FD16 b2 CNTR0/CNTR1 Notes 1: This bit is not provided in the 7477/7478 group. 2: This bit is not provided in the 7470/7471 group.
Interrupt enable bits Bits Address b0 00FE16 b1 00FE16 b2 00FE16 b3 00FE16 b6 (Note 1) 00FE16 b5 (Note 2) 00FE16 b6 (Note 2) 00FE16 b7 00FE16 b0 00FF16 b1 00FF16 b2 00FF16
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(1) Interrupt request bit The interrupt request bits are assigned to each bit of the Interrupt request register 1(IR1: Address 00FC16) and the Interrupt request register 2(IR2: Address 00FD16). If an interrupt request occurs, the corresponding interrupt request bit is set to "1." The interrupt request bit is held in the "1" state until the interrupt is accepted. After it is accepted, this bit is automatically cleared to "0." The interrupt request bit can be cleared to "0" by software but cannot be set to "1" by software. (2) Interrupt enable bit The interrupt enable bits are assigned to each bit of the Interrupt control register 1 (IE1: Address 00FE16) and the Interrupt control register 2 (IE2: Address 00FF16). The interrupt enable bit controls the acceptance of the corresponding interrupt. When the interrupt enable bit is "0," the acceptance of the corresponding interrupt is disabled. If an interrupt request occurs when this bit is "0," the corresponding interrupt request bit is set to "1," but this interrupt is not accepted. In this case, the interrupt request bit is cleared to "0" by software or remains in the "1" state until the interrupt enable bit is set to "1." When an interrupt enable bit is "1," the corresponding interrupt is enabled. If an interrupt request occurs when this bit is "1," this interrupt is accepted. (However, the interrupt disable flag that will be described later must be "0.") The interrupt enable bit can be cleared to "0" or set to "1" by software. (3) Interrupt disable flag The interrupt disable flag controls the acceptance of the interrupt, and is assigned to bit 2 of the Processor status register (PS). When this flag is "1," the interrupt disable state is provided. When this flag is "0," the acceptance of interrupt is enable state. This flag is set to "1" by the SEI instruction and cleared to "0" by the CLI instruction. This flag is set to "1" (interrupt disable state) automatically after the interrupt processing routine. To use a multi-interrupt, set this flag to "0" by using the CLI instruction in the interrupt processing routine. 2 Interrupt setting Set an interrupt according to the procedure shown below. 1The interrupt disable flag is set to "1." 2The interrupt enable bit is cleared to "0." 3For the INT interrupt or the CNTR interrupt, set the active edge in the Edge polarity selection register. Select one of the above interrupts in bit 4 of the Edge polarity selection register because the CNTR0 interrupt and the CNTR1 interrupt can not be used simultaneously. ( 0: CNTR0, 1: CNTR1 ) 4The request bit of interrupt used is cleared to "0." (Refer to "Table 1.11.2.") 5The enable bit of interrupt used is set to "1." (Refer to "Table 1.11.2.") 6The interrupt disable flag is cleared to "0."
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1.11.4 Notes on use (1) When using P30 to P33 as input ports, put the corresponding INT interrupt or the CNTR interrupt into a disable state. (2) Set the interrupt request bit and the interrupt enable bit for preparations for an interrupt in the following order. 1 Clear the interrupt request bit to "0." (No interrupt request) 2 Set the interrupt enable bit to "1." (Interrupt enabled) When using the INT interrupt or the CNTR interrupt, first set the interrupt detection edge and then set the above items 1 and 2. (Refer to (4) that will be described later.) (3) An interrupt request bit can be cleared to "0" by software, but is still remained at the value precedent to a change immediately after execution of the clear instruction. For this reason, when executing the BBC or BBS instruction after changing an interrupt request bit, first execute the interrupt request bit change instruction and then execute the BBC or BBS instruction after one instruction or more. (4) When the detection edge of the INT interrupt or that of the CNTR interrupt is switched, the corresponding interrupt request bit may be set to "1." Accordingly, perform setting referring to the register setting example shown in Figure 1.11.7.
Clear the corresponding interrupt enable bit to "0" Set the interrupt active edge Clear the corresponding interrupt request bit to "0" Execute one or more instructions (NOP instruction, and so on) Set the corresponding interrupt enable bit to "1"
Fig. 1.11.7 Example of register setting (5) Whether an interrupt is caused by the BRK instruction or not can be judged by the contents of the break flag of the Processor status register pushed on the stack area. q Break flag = "1" : An interrupt has been caused by the BRK instruction q Break flag = "0" : In case of the other interrupts Note: Make this judgment in the interrupt processing routine. (6) When an INT interrupt request is generated by executing the STP/WIT instruction in one of the following states, the stop mode/wait mode is released. q When the active edge of the INT interrupt is a rising edge and the INT pin input level is "H" q When the active edge of the INT interrupt is a falling edge and the INT pin input level is "L" Accordingly, when executing the STP/WIT instruction, it is necessary to consider the input level of the INT pin and the polarity of the INT edge. Examples of countermeasures for it are shown below. 1. An example of a countermeasure for the case where the stop mode/wait mode is released at the rising edge of the INT pin input level Point: To release the stop mode/wait mode normally, perform mode release processing in the INT interrupt processing routine only when the STP/WIT instruction was executed at the "L" INT pin input level.
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< Main routine > In the main routine, set the INT edge polarity according to the INT pin input level just precedent to execution of the STP/WIT instruction. 1 INT interrupt disable 2 q Select the falling edge when the INT pin input level is "H." q Select the rising edge when the INT pin input level is "L." 3 Clear the INT interrupt request bit to "0" and enable an INT interrupt after one instruction or more. 4 Clear the interrupt disable flag to "0." 5 Execute the STP/WIT instruction < INT interrupt processing routine > In the INT interrupt processing routine, change the active edge of the INT interrupt without performing release processing and proceed to the stop mode/wait mode in the case where the stop mode/wait mode is released by detecting a falling edge. q When the INT pin input level is "H" (when a rising edge is detected) Processing for releasing the stop mode/wait mode q When the INT pin input level is "L" (when a falling edge is detected) [1] Select the rising edge [2] Clear the INT interrupt request bit to "0" [3] Pop from stack [4] Perform 4 and 5 processing of the main routine. 2. An example of a countermeasure for the case where the stop mode/wait mode is released at the rising edge of the INT0 pin input level or the falling edge of the INT1 pin input level after the same signal is input to the INT0 pin and the INT1 pin. Point: Select the INT interrupt, by the main routine, that becomes a source of release of the stop mode/wait mode according to the INT pin input level just precedent to execution of the STP/WIT instruction. < Main routine > 1 INT0 and INT1 interrupt disable 2 Select the rising edge for the active edge of the INT0 interrupt. Select the falling edge for the active edge of the INT1 interrupt. 3 q When the INT pin input level is "H" Clear the INT1 interrupt request bit to "0" and enable the INT1 interrupt after one instruction or more. q When the INT pin input level is "L" Clear the INT0 interrupt request bit to "0" and enable the INT0 interrupt after one instruction or more. 4 Clear the interrupt disable flag to "0." 5 Execute the STP/WIT instruction. (7) In ordinary operation, if the pulse width of the INT input signal is 2 internal clocks f ( f(XIN)/2 ) or more by the built-in noise elimination circuit, it is accepted as an interrupt input. Input the INT input signal with a pulse width of 100 ns or more in the stop mode and the wait mode. Reference: As a hardware-level means to prevent incorrect interrupt processing due to noise, a noise elimination circuit is incorporated in the INT0 and INT1 pins so that no interrupt can be generated by an "H" pulse (when the rising edge is selected) or an "L" pulse (when a falling edge is selected) of one machine cycle or less in modes other than the stop mode and the wait mode. As a software-level means, the levels of the INT0 and INT1 pins are judged at the beginning of the interrupt processing routine.
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1.11.5 Related registers (1) Edge polarity selection register (EG: Address 00D416) The Edge polarity selection register selects an active edge of each INT interrupt and selects a source of interrupt. Figure 1.11.8 shows a structure of Edge polarity selection register.
Edge polarity selection register
b7 b6 b5 b4 b3 b2 b1 b0
Edge polarity selection register (EG) [Address 00D416] Name INT0 edge selection 0 bit B 1 INT1 edge selection bit 2 CNTR0 edge selection bit 3 CNTR1 edge selection bit 4 CNTR0/CNTR1 interrupt selection bit Function 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : CNTR0 1 : CNTR1
At reset
RW
0 0 0 0 0
5 INT1 source selection 0 : P31/INT1 bit (at STP or WIT 1 : P00 to P07 "L" level input instruction execution) (for key-on wake-up) 6, 7 Nothing is allocated for these bits. These are write disabled bits and are undefined at reading.
0
?
?!
Fig. 1.11.8 Structure of Edge polarity selection register
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1.11 Interrupts
(2) Interrupt request register 1 (IR1: Address 00FC16) Interrupt request register 2 (IR2: Address 00FD16) The Interrupt request register 1 and the Interrupt request register 2 consist of bits that indicate whether an interrupt request exists or not. Figure 1.11.9 shows a structure of the Interrupt request register 1 and Figure 1.11.10 shows a structure of the Interrupt request register 2.
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IR1) [Address 00FC16] B 0 1 2 3 4 5 Name Function
At reset
RW V V V V ?! V
0 : No interrupt request Timer 1 interrupt 1 : Interrupt requested request bit Timer 2 interrupt 0 : No interrupt request request bit 1 : Interrupt requested 0 : No interrupt request Timer 3 interrupt 1 : Interrupt requested request bit Timer 4 interrupt 0 : No interrupt request request bit 1 : Interrupt requested Nothing is allocated for this bit. This is write disabled bit and is undefined at reading. Serial I/O receive interrupt request bit (7477/7478 group)(Note) Serial I/O interrupt request bit (7470/7471group) Serial I/O transmit interrupt request bit (7477/7478 group) A-D conversion completion interrupt request bit 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested
0 0 0 0 ?
0
6
0
V
7
0 : No interrupt request 1 : Interrupt requested
0
V
Note: In the 7470/7471group, nothing is allocated for bit 5. This is write disabled bit and is undefined at reading. V : "0" is set by software, but not "1."
Fig. 1.11.9 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IR2) [Address 00FD16] B 0 Name Function
At reset
RW V V V ?!
INT0 interrupt request 0 : No interrupt request 1 : Interrupt requested bit 1 INT1 interrupt request 0 : No interrupt request bit 1 : Interrupt requested 0 : No interrupt request 2 CNTR0 or CNTR1 interrupt request bit 1 : Interrupt requested 3 Nothing is allocated for these bits. There are write to disabled bits and are undefined at reading. 7 V : "0" is set by software, but not "1."
0 0 0 ?
Fig. 1.11.10 Structure of Interrupt request register 2
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(3) Interrupt control register 1 (IE1: Address 00FE16) Interrupt control register 2 (IE2: Address 00FF16) The Interrupt control register 1 and the Interrupt control register 2 control the acceptance of interrupt by source. Figure 1.11.11 shows a structure of the Interrupt control register 1 and Figure 1.11.12 shows a structure of an Interrupt control register 2.
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (IE1) [Address 00FE16] B 0 1 2 3 4 5 Name Function
At reset
RW
0 : Interrupt disabled Timer 1 interrupt 1 : Interrupt enabled enable bit 0 : Interrupt disabled Timer 2 interrupt 1 : Interrupt enabled enable bit 0 : Interrupt disabled Timer 3 interrupt 1 : Interrupt enabled enable bit Timer 4 interrupt 0 : Interrupt disabled enable bit 1 : Interrupt enabled Nothing is allocated for this bit. This is write disabled bit and is undefined at reading. Serial I/O receive interrupt enable bit (7477/7478 group) (Note) Serial I/O interrupt enable bit (7470/7471 group) Serial I/O transmit interrupt enable bit (7477/7478 group) A-D conversion completion interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
0 0 0 0 ? 0 ?!
6
0
7
0 : Interrupt disabled 1 : Interrupt enabled
0
Note: In the 7470/7471 group, Nothing is allocated for bit 5. This is write disabled bit and undefined at reading.
Fig. 1.11.11 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (IE2) [Address 00FF16] B 0 Name Function
At reset
RW
0 : Interrupt disabled INT0 interrupt enable 1 : Interrupt enabled bit 1 INT1 interrupt enable 0 : Interrupt disabled bit 1 : Interrupt enabled 0 : Interrupt disabled 2 CNTR0 or CNTR1 interrupt enable bit 1 : Interrupt enabled Nothing is allocated for these bits. There are write 3 to disabled bits and are undefined at reading. 7
0 0 0 ? ?!
Fig. 1.11.12 Structure of Interrupt control register 2
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1.12 Timers
1.12 Timers
The 7470/7471/7477/7478 group has four 8-bit timers (Timer 1, Timer 2, Timer 3 and Timer 4) with an 8bit timer latch. The division ratio of the timer is 1/(n+1) when the contents of the timer latch are n (n:0 to 255). For the timer, the following modes can be selected by software setting. * * * * * Timer mode Event counter mode Pulse output mode External pulse width measurement mode PWM mode
Table 1.12.1 shows the modes of each timer and Figure 1.12.1 shows a timer block diagram.
Table 1.12.1 Modes of each timer Mode Timer Timer Timer Timer Timer 1 2 3 4 Timer mode Event counter mode ! Pulse output mode ! ! External pulse width measurement mode ! ! ! PWM mode ! !
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XCIN 1/2 XIN 1/2 1/8 CM7 T12M2 T12M0 EG2 Port latch P12/T0 T12M1 TM20 1/2 T12M3
Data bus
Timer 1 latch (8) Timer 1 (8)
P32/CNTR0
Timer 1 interrupt request
Timer 2 latch (8)
T12M6, T12M7
T12M4 T12M5
Timer 2 (8)
TM26 T34M1 T34M2 T34M0
1/4 1/8 1/16
Timer 2 interrupt request
Timer 3 latch (8) Timer 3 (8)
P33/CNTR1
EG3
Timer 3 interrupt request
T34M4 T34M5
Timer 4 latch (8) Timer 4 (8)
Timer 4 interrupt request
Port latch P13/T1 P33/CNTR1
EG4
T34M6 T34M3 TM27 1/2
F/F
T34M7
EG3 EG2
TM21 C
D3 D2 D1 D0 Q3 Q2 Q1 Q0
P32/CNTR0 EG1 P31/INT1 EG0 P30/INT0
Notes 1: The 7470/7477 group is not provided with the XCIN pin. 2: The number (ex. EG 3) described the right side of the register represents the bit number of the register.
Fig. 1.12.1 Timer block diagram
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1.12.1 Operation description In a write operation, the timer latch is specified at the same time when the timer is specified. If the timer is set to n16, the timer latch is also set to n16 (n: 0016 to FF16). After the timer starts to count, 1 the timer value is counted down as n16 (n-1)16 (n-2)16 ... 116 016 FF16 at each rise of the count source. 2 At the next rise of the count source after "FF16," q (n-1)16 resulting from decrementing 1 from the timer latch value is set (reloaded) in the timer and then the timer continues to count. q When an overflow occurs, the interrupt request bit is set to "1." Note: When the interrupt is accepted, the interrupt request bit changes from "1" to "0." It can be clearned to "0" but cannot be set to "1" by software. Figure 1.12.2 shows a timer count timing.
Count operation stop Count stop bit
Count start
Writing to timer Timer count source
Reload
Value of timer
!!16
n16
(n-1)16 (n-2)16 (n-3)16
116
016
FF16 (n-1)16
Read value of timer
(!!+1)16
n16
(n-1)16 (n-2)16 (n-3)16
116
016
FF16 (n-1)16
Timer interrupt request bit
Fig. 1.12.2 Timer count timing
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1.12.2 Description of modes (1) Timer mode The operations of the timer modes are as explained below. 1 Start of count operation When the count stop bit is cleared to "0," a count operation starts. When there is a count source input, the contents of the timer are decremented by 1. Note: Because the count stop bit is "0" immediately after reset release, the count operation is automatically started after reset release. 2 Reload operation When the timer overflows, the value resulting from decrementing 1 from the contents of the timer latch is transferred (reloaded) to the timer. 3 Interrupt operation 2 Timer interrupt When the timer overflows, an interrupt request occurs, so that the interrupt request bit is set to "1." The acceptance of interrupt is controlled by the interrupt enable bit of each timer. 4 Stop of count operation When the counter stop bit is set to "1" by software, the count operation stops. (The count operation continues until the count stop bit is set to "1.") Figure 1.12.3 shows an example of timer mode operation.
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Count period Count period T(s) = 1 / count source frequency ! (the timer initial value + 1)
Timer mode operation example
* OF: Overflow * RL: Reload * n: Timer initial value
Timer 1 count stop bit Timer 1 count source "1" is written "0" is written
RL
RL
RL
RL
Count stop Count restart
Value of timer 1
(n-1)16
Down count
OF
OF
OF
OF
FF16
T
Timer 1 interrupt request bit A Timer 1 interrupt enable bit A A A
Time
A : * Clearing by writing "0" to the timer interrupt request bit.
* Clearing by accepting the timer interrupt request when the timer interrupt enable bit is "1."
Fig. 1.12.3 Example of timer mode operation
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[Setting method] 1 Set a value to be used according to the count source setting for timers. The count operation of the timer is stopped. Refer to "Table 1.12.2 Setting for count stop." Table 1.12.2 Setting for count stop Setting item Timer 12 mode register (T12M: Address 00F816) b4 b0 Timer - 1 Timer 1 1 - Timer 2 Timer 3 - - Timer 4
Timer 34 mode register (T34M: Address 00F916) b3 b0 - - 1 - 1 -
2 Count source selecting Select a count source according to the count source setting for timers shown in Table 1.12.3 to Table 1.12.6. Note that selectable count sources are different among timers. Because the 7470/7477 group is not provided with an XCIN pin, do not select f(XCIN) as a count source.
Table 1.12.3 Setting for timer 1 count source Setting item CPU mode register Timer 12 mode register Count source (CM: Address 00FB16) (T12M: Address 00F816) to be selected b7 b2 b1 f(XIN)/16 0 0 f(XCIN) - (Note) 1 0 f(XCIN)/16 1 0 External clock input from - - 1 CNTR0 pin. Note: When f(XCIN) is selected as a timer count source, f(XIN) or f(XCIN) can be selected as a system clock.
Table 1.12.4 Setting for timer 2 count source CPU mode register Setting item (CM: Address 00FB16) Count source to be selected b7 f(XIN)/16 f(XIN)/64 0 f(XIN)/128 f(XIN)/256 f(XCIN)/16 f(XCIN)/64 1 f(XCIN)/128 f(XCIN)/256 Timer 1 overflow signal -
Timer 12 mode register (T12M: Address 00F816) b7 b6 b5 0 0 0 1 1 0 1 1 0 0 0 0 1 1 0 1 1 - - 1
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Table 1.12.5 Setting for Timer 3 count source Setting item CPU mode register Timer mode register 2 Timer 34 mode register Count source (CM: Address 00FB16) (TM2: Address 00FA16) (T34M: Address 00F916) to be selected b7 b6 b2 b1 f(XIN)/16 0 0 0 (Note) f(XCIN) - - 0 1 f(XCIN)/16 1 0 0 Timer 1 overflow signal 0 - 1 0 Timer 2 overflow signal 1 External clock input from - - 1 1 CNTR1 pin Note: When f(XCIN) is selected as a timer count source, f(XIN) or f(XCIN) can be selected as a system clock.
Table 1.12.6 Setting for Timer 4 count source Setting item Timer mode register 2 Timer 34 mode register CPU mode register Count source (CM: Address 00FB16) (TM2: Address 00FA16) (T34M: Address 00F916) to be selected b7 b6 b5 b4 b6 f(XIN)/16 0 - 0 1 f(XCIN)/16 1 0 1 0 Timer 1 overflow signal 1 (Note) (Note) Timer 2 overflow signal 0 - 0 0 Timer 3 overflow signal External clock input from - 1 1 CNTR1 pin Note: If the Timer 1 overflow signal is selected as a Timer 2 count source at [b5,b4] = [1,0], the Timer 4 count source becomes the Timer 1 overflow signal regardless of bit 6 of Timer mode register 2.
3 Set a count value in the timer. Refer to "Table 1.12.7 Address allocation for timer."
Table 1.12.7 Address allocation of timer Timer Address Timer 1(T1) 00F016 Timer 2(T2) 00F116 Timer 3(T3) 00F216 Timer 4(T4) 00F316
4 When a value is set according to the count start setting shown in Table 1.12.8, the timer starts to count. Table 1.12.8 Count start setting Setting item Timer 12 mode register (T12M: Address 00F816) b4 b0 Timer - 0 Timer 1 0 - Timer 2 Timer 3 - - Timer 4
Timer 34 mode register (T34M: Address 00F916) b3 b0 - - 0 - 0 -
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(2) Event counter mode In the event counter mode, the same operations as those in the timer mode are performed, with the exception that the signal input from the CNTR0 pin becomes a count source of Timer 1 and the signal input from the CNTR1 pin becomes a count source of Timer 3 and Timer 4. The operation in the event counter mode are described below. 1 Start of count operation After the count stop bit is cleared to "0," a count operation starts. Each time a count source is input, the contents of the timer are decremented by 1. For the active edge of count source, a rise or a fall can be selected by the edge polarity selection register (address 00D416). Note: Because the count stop bit is "0" immediately after reset release, the count operation is automatically started after reset release but the count source is not a CNTR pin input (operates as the timer mode). 2 Reload operation When the timer overflows, the value resulting from decrementing 1 from the contents of the timer latch is transferred (reloaded) to the timer. 3 Interrupt operation 2 Timer interrupt When the timer overflows, an interrupt request occurs, so that the interrupt request bit is set to "1." The acceptance of interrupt is controlled by the interrupt enable bit of each timer. 2 CNTR interrupt An interrupt request is generated from the edge of the count source input from the CNTR0 pin or the CNTR1 pin, so that the interrupt request is set to "1." The acceptance of interrupt is controlled by the interrupt enable bit of each timer. The edge polarity selection register selects an active edge of count source and a CNTR0/ CNTR1 interrupt. 4 Stop of count operation When the counter stop bit is set to "1" by software, the count operation stops. (The count operation continues until "1" is set in the count stop bit.) Figure 1.12.4 shows an example of event counter mode operation.
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Count period Count period T(s) = 1 / count source frequency ! (the timer initial value + 1)
Event counter mode operation example
* OF: Overflow * RL: Reload * n: Timer initial value
Timer 1 count stop bit "0" is written "1" is written
Count source (CNTR0 pin) to B Count stop
RL RL RL
Down count Value of timer 1
Count restart
(n-1)16
OF
OF
OF
FF16
T
Time
CNTR edge selection bit
In this example, the CNTR interrupt request occurs at rising edge of the count source. In this example, each CNTR interrupt request does not occur during executing the CNTR interrupt processing routine.
CNTR interrupt request bit A CNTR interrupt enable bit B Timer 1 interrupt request bit A Timer 1 interrupt enable bit A : * Clearing by writing "0" to the Timer 1 and CNTR interrupt request bits. * Clearing by accepting the Timer 1 and CNTR interrupt requests when the timer 1 and CNTR interrupt enable bits are "1." A A A A A A A A A A A A A
Fig. 1.12.4 Example of event counter mode operation
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[Setting method] 1 The count operation of a timer to be used is stopped. Refer to "Table 1.12.2 Setting for count stop." 2 Select a count source according to the event counter mode setting shown in Table1.12.9. 3 Set a count value in the timer. Refer to "Table 1.12.7 Address allocation of timer." 4 Start a count operation of timer to be used. Refer to "Table 1.12.8 Count start setting." Table. 1.12.9 Event counter mode setting Timer 34 mode register Timer Edge polarity selection register Timer 12 mode register Count (T34M: Address 00F916) to be (EG: Address 00D416) (T12M: Address 00F816) source used b3 b1 b6 b2 b1 b2 b5 b4 Timer 1 CNTR0 - Select (Note) 1 - Timer 3 Select 1 1 - - - CNTR1 0 Timer 4 (Note) - 1 1 Note: 0: The falling edge (An input, when it is inverted, becomes a count source). 1: The rising edge (An input itself becomes a count source). (3) Pulse output mode The pulse output mode is a mode resulting from adding a pulse output operation to a timer mode operation. In this mode, a pulse whose polarity is inverted at each overflow is output from the T0 (Timer 1 overflow signal/2) pin and the T1 (Timer 4 overflow signal/2) pin. The operations in the pulse output mode are described below. 1 Start of count operation After the count stop bit is set to "0," a count operation starts. Each time a count source is input, the contents of the timer are decremented by 1. Note: Because the count stop bit is "0" immediately after reset release, the count operation is automatically started immediately after reset release but no pulse is output. 2 Reload operation When the timer overflows, the value resulting from decrementing 1 from the contents of the timer latch is transferred (reloaded) to the timer. 3 Pulse is output * A pulse whose polarity is inverted at each overflow is output from the T0 pin and the T1 pin. * "H" or "L" can be selected as a level for a start of pulse output by each division flip-flop. * A pulse output is started from the moment when the T0 or T1 pin output is selected by the Timer 12 mode register or the Timer 34 mode register. 4 Interrupt operation 2 Timer interrupt When the timer overflows, an interrupt request occurs, so that the interrupt request bit is set. The acceptance of interrupt is controlled by the interrupt enable bit of each timer. 5 Stop of count operation When "1" is set in the counter stop bit by software, the count operation stops. (The count operation continues until "1" is set in the count stop bit.) Figure 1.12.5 shows a example of pulse output mode operation.
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Count period Count period T(s) = 1 / count source frequency ! (the timer initial value + 1)
Pulse output mode operation example
* OF: Overflow * RL: Reload * n: Timer initial value
Timer 1 count stop bit Timer 1 count source Writing "1" Writing "0"
RL
RL
RL
RL
Count stop Count restart
(n-1)16
Value of timer 1
Down count
OF
OF
OF
OF
FF16
T0 output selected
T
Time
T0 pin
Setting to output port
Initial value "0"
Timer FF register bit 0
Timer 1 interrupt request bit A Timer 1 interrupt enable bit A A A
A : * Clearing by writing "0" to the Timer 1 interrupt request bit. * Clearing by accepting the Timer 1 interrupt request when the Timer 1 interrupt enable bit is "1."
Fig. 1.12.5 Example of pulse output mode operation
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[Setting method] 1 The count operation of a timer to be used is stopped. Refer to "Table 1.12.2 Setting for count stop." 2 Set the pulse output mode according to the pulse output mode initial value setting shown in Table 1.12.10. However, set the timer FF register after setting timer mode register 2.
Table 1.12.10 Pulse output mode initial value setting Setting item Timer mode register 2 (TM2: Address 00FA16) b0 b1 Timer to be used 1 - Timer 1 - 1 Timer 4 Note: 0: The initial value becomes "0." 1: The initial value becomes "1."
Timer FF mode register (TF: Address 00F716) b0 b1 Select (Note) - - Select (Note)
3 Set the pulse output mode according to the pulse output mode setting shown in Table 1.12.11. The T0 output port and the T1 output port are used in common with P12 and P13, respectively. Accordingly, set the bit 2 and bit 3 of the port P1 direction register to the output mode. Table 1.12.11 Pulse output mode setting Timer 12 mode register Output pin Timer (T12M: Address 00F816) b3 T0 Timer 1 Timer 1 overflow 1 signal / 2 T1 Timer 4 Timer 4 overflow - signal / 2 4 Set a count value in Timer 1 (T0 output) and Timer 4 (T1 output). 5 When a value is set according to the count start setting shown in Table 1.12.8, the timer starts to count. Note: When resetting a value in the Timer FF register, be sure to observe the setting methods of the above items 1 to 5.
Timer 34 mode register (T34M: Address 00F916) b7 b6 -
1
0
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(4) External pulse width measurement mode The external pulse width measurement mode is used to measure a pulse width ("H" or "L") input from the CNTR0 or CNTR1 pin. The operations in the external pulse width measuring mode are described below. 1 Start of count operation After the count stop bit is cleared to "0," a count operation starts. Each time a count source is input, the contents of the timer are decremented by 1. Note: Because the count stop bit is "0" immediately after reset release, the count operation is automatically started after reset release but the count source is not a CNTR pin input. At this time, the external pulse width measurement mode is not provided. 2 Reload operation When the timer overflows, the value resulting from decrementing 1 from the contents of the timer latch is transferred (reloaded) to the timer. 3 External pulse width measurement mode q The "H" or "L" level of a pulse can be selected as a pulse measuring period by the Edge polarity selection register. q The difference between the initial value of the timer and the counter value at a count stop becomes a measured pulse width. q A reload operation by reading the count value is not performed automatically. To perform measurement continuously, re-set the initial value by software. 4 Interrupt operation 2Timer interrupt When the timer overflows, an interrupt request occurs, so that the interrupt request bit is set to "1." The acceptance of interrupt is controlled by the interrupt enable bit of each timer. 2CNTR interrupt An interrupt request is generated from the edge of the pulse input from the CNTR0 pin or the CNTR1 pin, so that the interrupt request bit is set to "1." Interrupt acceptance is controlled by the interrupt enable bit. The pulse active edge and the CNTR0/CNTR1 interrupt are selected by the Edge polarity selection register. 5 Stop of count operation The count operation terminates at the falling edge (at "H" level pulse width measurement) or the falling edge ("L" level pulse width measurement) of the CNTR pin input. This operation is also terminated by setting "1" in the count stop bit by software. Figure 1.12.6 shows an example of the operation of the external pulse width measurement mode.
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Pulse width Pulse width H(s) = 1 / count source frequency ! (the timer initial value - count value at count stop)
External pulse width measurement mode operation example
* n: Timer initial value * m: Count value at count stop
Timer 4 count stop bit Timer 4 count source
CNTR0 pin
CNTR edge selection bit Setting the initial value to timer
Count start
Setting the initial value to timer
Count start
(n-1)16
Value of timer 4
Count stop
m16
FF16
H
CNTR interrupt request bit A
H
Time
CNTR interrupt enable bit
Timer 4 interrupt request bit Timer 4 interrupt enable bit
A : * Clearing by writing "0" to the CNTR interrupt request bit. * Clearing by accepting the CNTR interrupt request when the CNTR interrupt enable bit is "1." V : When the CNTR edge selection bit is "0," "H" level width of the input pulse is measured.
Fig. 1.12.6 Example of operation of external pulse width measurement mode
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[Setting method] 1 The count operation of Timer 4 is stopped by setting bit 3 of the Timer 34 mode register to "1." Refer to "Table 1.12.2 Setting for count stop." 2 Set each register according to the external pulse width measuring mode setting shown in Table 1.12.12. 3 Set a value in the timer. Refer to "Table 1.12.7 Address allocation of timer." 4 Clear bit 3 of the Timer 34 mode register to "0" and start the count of timer 4. Refer to "Table 1.12.8 Count start setting." Table 1.12.12 External pulse width measurement mode setting Timer 34 mode register Timer to Measuring (T34M: Address 00F816) be used pulse b6 b5 b4 CNTR0 Timer 4 CNTR1 1 b5 b4 0 0 : Timer 3 overflow signal 0 1 : f (XIN)/16 or f (XCIN)/16 1 0 : Timer 1 or Timer 2 overflow signal 1 1 : CNTR1 pin (Note 2)
Edge polarity selection register (EG: Address 00D416) b3 b4 b2 0 - Select (Note 1)
1
Select (Note 1)
-
Notes 1: 0: The count source is counted while the external pulse is "H." 1: The count source is counted while the external pulse is "L." 2: When the measured pulse is the CNTR1 pin, do not select the CNTR1 as the count source of Timer 4.
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(5) PWM mode In the PWM mode, a PWM waveform is output from the T1 pin by using Timer 3 and Timer 4. The operations in the PWM mode are described below. 1 Start of count operation After the count stop bit is cleared to "0," a count operation starts. Each time a count source is input, the contents of the timer are decremented by 1. Note: The count stop bit is "0" immediately after reset release. Accordingly, a count operation is automatically started immediately after reset release but no PWM waveform is output because the PWM mode is not provided. 2 Reload operation When the timer overflows, the value resulting from decrementing 1 from the contents of the timer latch is transferred (reloaded) to the timer. 3 PWM output In the PWM mode, the following operations are performed. 1 When the PWM mode is started * The PWM waveform starts with "L." * Timer 3: Counts the count sources. * Timer 4: Stops 2When Timer 3 overflows * The PWM waveform goes to "H." * Timer 3: Stops. * Timer 4: Counts the count sources. 3 When Timer 4 overflows * The PWM waveform goes to "L." * Timer 3: Counts the count sources. * Timer 4: Stops.
The "L" width of the PWM waveform is set in Timer 3 and the "H" width is set in Timer 4. 4 Interrupt operation 2Timer interrupt When the timer overflows, an interrupt request occurs, so that the interrupt request bit is set to "1." The acceptance of interrupt is controlled by the interrupt enable bit of each timer. 5 Stop of count operation When the counter stop bit is set to "1" by software, the count operation stops. (The count operation continues until the count stop bit is set to "1.") Figure 1.12.7 shows an example of the operation of the PWM output mode.
To be repeated
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Count period Timer 3 count period Timer 4 count period T3(s) = 1 / timer 3 count source frequency ! (the timer 3 initial value + 1) T4(s) = 1 / timer 4 count source frequency ! (the timer 4 initial value + 1)
PWM mode operation example
* OF: Overflow * RL: Reload * n: Timer 3 initial value * m: Timer 4 initial value
Timer 3 count source
To B To B ' To B " (Note)
RL
RL
RL (Note)
(n-1)16
Value of timer 3
OF
OF
OF
FF16
T3
T3
"1" is written "0" is written
Time
Timer 4 count stop bit
Timer 4 count source To C RL (Note) To C ' RL (Note)
Count stop Count restart
(m-1)16
Value of timer 4
OF
OF
FF16
Setting to output port T1 pin
PWM output mode selected B'
T4
C' B"
T4
Time
A
A B' B"
A
Timer 3 interrupt request bit Timer 3 interrupt enable bit
B
A C C'
A
Timer 4 interrupt request bit Timer 4 interrupt enable bit
A : * Clearing by writing "0" to the Timer 3 and Timer 4 interrupt request bits. * Clearing by accepting the interrupt request when the Timer 3 and Timer 4 interrupt enable bits are "1." Note: Timer 3 and Timer 4 do not accept count sources in the period from an overflow of the respective timer till an overflow of the other timer. Because the timer read value changes at the fall of a count source, the read value in this period remains "FF16".
Fig.1.12.7 Example of operation of PWM output mode 1-78
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[Setting method] 1 The count operation of a timer to be used is stopped. Refer to "Table 1.12.2 Setting for count stop." 2 Port P13 is put into the output mode by setting bit 3 of the port P1 direction register (address 00C116) to "1." 3 Select a count source of Timer 3 and Timer 4. However, don't select the Timer 3 overflow signal as a count source of Timer 4. Refer to "Table 1.12.5 Setting for Timer 3 count source" and "Table 1.12.6 Setting for Timer 4 count source." 4 Set the bit 7 of the Timer 34 mode register to "1." 5 Set a value in the timer. Refer to "Table 1.12.7 Address allocation of timer." 6 Set the bit 7 of the Timer mode register 2 to "1." 7 The count operation of a timer to be used is started. Refer to "Table 1.12.8 Count start setting." Note: When the PWM mode is started from another mode, the PWM waveform starts with the "L" state. 1.12.3 Input latch function There is a function which latches the levels of the INT0, INT1, CNTR0 and CNTR1 pins to the input latch register when Timer 4 overflows. Using this function permits knowing the level of each pin accurately the moment when a Timer 4 overflow occurs. The polarity of each pin is selected by the edge polarity selection register, the level or the reverse level of each pin are latched to the Input latch register. Table 1.12.13 shows the Edge polarity selection register setting related to the input latch. Table 1.12.13 Edge polarity selection register setting Input latch register (ILR: Address 00D616) b0 b1 b2 b3 Latched contents INT0 pin level Reverse level on INT1 pin level Reverse level on CNTR0 pin level Reverse level on CNTR1 pin level Reverse level on Edge polarity selection register (EG: Address 00D416) b3 b2 b1 b0 1 - - - 0 1 - - - 0 1 - - - 0 1 - - - 0
INT0 pin INT1 pin CNTR0 pin CNTR1 pin
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1.12.4 Updating of contents of Timer and Timer latch After data is written to the Timer, the contents of the Timer and the Timer latch are updated. 2 Timer 1 and Timer 2 When data is written to the Timer, this data is set in the Timer and the Timer latch at the same time. As a result, after data is written to the Timer which is in count operation, the count period becomes invalid. Figure 1.12.8 shows an example of updating of the contents of Timer 1, Time 2 and Timer latch.
Example of updating of Timer 1
* OF: Overflow * RL: Reload * n: Timer 1 initial value before updating * m: Timer 1 initial value after updating
Writing "m16" to timer 1
RL
m16 (m-1)16
Value of timer 1
RL
RL
(n-1)16
OF
OF
OF
FF16 Incorrect count period Timer 1 interrupt request bit
A A A
Time
Timer 1 interrupt enable bit
A : * Clearing by writing "0" to the Timer 1 interrupt request bit.
* Clearing by accepting the Timer 1 interrupt request when the Timer 1 interrupt enable bit is "1."
Fig. 1.12.8 Example of updating of Timer 1, Timer 2 and Timer latch
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2 Timer 3 and Timer 4 q At PWM mode After data is written to the Timer which is in count operation, the written data is set only in the Timer latch but not in the Timer. After that, when the Timer overflows, a value resulting from decrementing 1 from the value of the Timer latch is written in the Timer. When data is written to the Timer being at a stop, the written data is set in both Timer and Timer latch. q In modes other than the PWM mode The same operation as "Timer 1 and Timer 2" described in the previous item is performed. Figure 1.12.9 shows an example of updating of the contents of Timer 3, Time 4 and Timer latch in PWM mode.
Example of updating of Timer at PWM mode
* OF: Overflow * RL: Reload * n: Timer 3 initial value before updating * m: Timer 3 initial value after updating * k: Timer 4 initial value before updating * h: Timer 4 initial value after updaiting
Writing "m16" to timer 3
RL
m16 (m-1)16
Value of timer 3
RL
(n-1)16
OF
OF
FF16 Count of timer 3 Count of timer 3 by rewriting timer value
Time
RL
(h-1)16
Value of timer 4
Writing "h16" to timer 4
RL
(k-1)16
OF
OF
FF16 Count of timer 4
Timer 3 interrupt request bit Timer 4 Timer 3 interrupt Timer 3 interrupt enable bit Timer 4
Count of timer 4 by rewriting timer value Time
A
Timer 4 interrupt
A
Timer 3 interrupt
A
A : * Clearing by writing "0" to the Timer 3 or Timer 4 interrupt request bit. * Clearing by accepting the Timer 3 and the Timer 4 interrupt request when the Timer 3 and the Timer 4 interrupt enable bit is "1."
Fig. 1.12.9 Example of updating of Timer 3, Timer 4 and Timer latch in PWM mode
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1.12.5 Notes on use (1) The contents of the Timer 12 mode register (T12M: Address 00F816) and the Timer 34 mode register (T34M: Address 00F916) become "0016" at reset and each timer performs a count operation. (2) Figure 1.12.10 shows the relation between Timer value change timing and read value change timing. The Timer value changes at the rise of the count source, while the read value changes at the fall of the count source. Accordingly, the read value may be larger than the real timer value by "1."
Example: Writing "9916" into Timer 1
Timer count source
Timer value
0116
0016
FF16
9816
9716
Timer read value
0216
0116
0016
FF16
9816
9716
Interrupt request bit
Fig. 1.12.10 Relation between timer value change timing and read value change timing
(3) To select the CNTR pin input as Timer count source, the frequency of the CNTR count source should satisfy the condition shown in Table 1.12.14. Table 1.12.14 Frequency of CNTR Frequency of the CNTR count source Main clock Upper boundary Lower boundary 4MHz 1MHz There is no 8MHz 2MHz special restriction.
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1.12.6 Related registers (1) Timer 1, Timer 2, Timer 3, Timer 4 (T1 to T4: Address 00F016 to 00F316) Each Timer is a register consisting of 8 bits. Read The contents (count value) of the Timer are read by reading the timer. Write When time. When is set Refer
data is written to the Timer, this data is set in the Timer and the Timer latch at the same data is written into the Timer being in count operation in the PWM mode, the written data only in the Timer latch. to "1.12.4 Updating of contents of Timer and Timer latch."
VTimer latch The Timer latch is a register that holds a value to be automatically transferred (reloaded) to the Timer as its initial value when the Timer overflows. It is impossible to read the contents of the Timer latch. Figure 1.12.11 shows a structure of Timer.
Timers 1 to 4
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1, Timer 2, Timer 3, Timer 4 (T1, T2, T3, T4) [Address 00F016, 00F116, 00F216, 00F316] B Function
At reset
RW
0 *Set "0016 to FF16." to *The value is decremented by 1 each time a 7 count source is input. *Each Timer values are set to the respective counter. *The count values are read out by reading the respective timer. Note : Timers 1 and 2 are undefined. Timer 3 is "FF16." Timer 4 is "0716."
(Note)
Fig. 1.12.11 Structure of Timers 1 to 4
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(2) Timer 12 mode register (T12M: Address 00F816) The Timer 12 mode register is a register consisting of bits that control a Timer count source and a count operation. Figure 1.12.12 shows a structure of Timer 12 mode register.
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 12 mode register (T12M) [Address 00F816] B 0 Name Function 0 : Count start 1 : Count stop 0 : Internal clock (Note 1) 1 : P32/CNTR0 external clock 0 : f(XIN)/16 or f(XCIN)/16 1 : f(XCIN) (Note 2) 0 : P12 port output 1 : T0(Timer 1 overflow divided by 2) 0 : Count start 1 : Count stop 0 : Internal clock (Note 1) 1 : Timer 1 overflow signal
b7 b6
At reset
RW
Timer 1 count stop bit 1 Timer 1 count source selection bit 2 Timer 1 internal clock source selection bit P12/T0 port output selection bit
0 0 0
3
0 0 0
4 Timer 2 count stop bit 5 Timer 2 count source selection bit
6, 7 Timer 2 internal clock source selection bits 0 0 : f(XIN)/16 or f(XCIN)/16 0 1 : f(XIN)/64 or f(XCIN)/64 1 0 : f(XIN)/128 or f(XCIN)/128 1 1 : f(XIN)/256 or f(XCIN)/256 (Note 3)
0
Notes 1: In the 7470/7477 group, the internal clock is f(X IN)/16. 2: Since the 7470/7477 group is not provided the sub-clock generating circuit, f(XCIN) cannot be used. Fix this bit to "0." 3: Since the 7470/7477 group is not provided the sub-clock generating circuit, f(XCIN) cannot be used.
Fig. 1.12.12 Structure of Timer 12 mode register
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1.12 Timers
(3) Timer 34 mode register (T34M: Address 00F916) The Timer 34 mode register is a register consisting of bits that control a timer count source and a count operation. Figure 1.12.13 shows a structure of Timer 34 mode register.
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 34 mode register (T34M) [Address 00F916] B 0 Name Function 0 : Count start 1 : Count stop
b2 b1
At reset
RW
Timer 3 count stop bit 1, 2 Timer 3 count source selection bits
0
0 0 : f(XIN)/16 or f(XCIN)/16 0 1 : f(XCIN) 1 0 : Timer 1 overflow or
Timer 2 overflow 1 1 : P33/CNTR1 external clock (Note 2) 3 Timer 4 count stop bit 0 : Count start 1 : Count stop
b4 b3
0
0
4, 5 Timer 4 count source selection bits
0 0 : Timer 3 overflow 0 1 : f(XIN)/16 or f(XCIN)/16 1 0 : Timer 1 overflow or
0
Timer 2 overflow 1 1 : P33/CNTR1 external clock (Notes 1, 2) 6 Timer 4 pulse width measurement mode selection bit P13/T1 port output selection bit 0 : Timer mode 1 : External pulse width measurement mode 0 : P13 port 1 : T1(Timer 4 overflow divided
by 2 or PWM output)
0
7
0
Notes 1: When Timer 1 overflow is selected as a Timer 2 count source, the Timer 4 count source is the Timer 1 overflow regardless of the value of bit 6 of the Timer mode register 2. 2: Since the 7470/7477 group is not provided the sub-clock generating circuit, f(X CIN) cannot be used.
Fig. 1.12.13 Structure of Timer 34 mode register
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(4) Timer mode register 2 (TM2: Address 00FA16) The Timer mode register 2 consists of bits that control a mode selection and a count source selection. Figure 1.12.14 shows a structure of Timer mode register 2.
Timer mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer mode register 2 (TM2) [Address 00FA16] B 0 Name Function
At reset
RW
0 : Set disable Timer 1 overflow FF 1 : Set enable set enable bit 0 : Set disable 1 Timer 4 overflow FF set enable bit 1 : Set enable Nothing is allocated for these bits. These are 2 to write disabled bits and are undefined at reading. 5 6 7 Timer 3, timer 4 count overflow signal selection bit Timer 3, timer 4 function selection bit 0 : Timer 1 overflow 1 : Timer 2 overflow 0 : Ordinary mode 1 : PWM mode
0 0 ? ?!
0 0
Fig. 1.12.14 Structure of Timer mode register 2 (5) Timer FF register (TF: Address 00F716) The Timer FF register consists of bits that are used for initialization in the pulse output mode. Figure 1.12.15 shows a structure of Timer FF register.
Timer FF register
b7 b6 b5 b4 b3 b2 b1 b0
Timer FF register (TF) [Address 00F716] B 0 1 2 to 7 Name Timer 1 division flip-flop Timer 4 division flip-flop Function 0 : Initial value is "0" 1 : Initial value is "1" 0 : Initial value is "0" 1 : Initial value is "1"
At reset
RW
0 0 ? ?!
Nothing is allocated for these bits. These are write disabled bits and are undefined at reading.
Fig. 1.12.15 Structure of Timer FF register
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(6) Input latch register (ILR: Address 00D616) The Input latch register consists of bits that latch the levels of the INT0, INT1, CNTR0 and CNTR1 pins when the Timer 4 overflows. Figure 1.12.16 shows a structure of Input latch register.
Input latch register
b7 b6 b5 b4 b3 b2 b1 b0
Input latch register (ILR) [Address 00D616] B Name Function
When b0 of EG (Note) is "0": reverse level on INT0 pin When b0 of EG (Note) is "1": level on INT0 pin
At reset
RW
0 P30/INT0 latch bit
?
!
1 P31/INT1 latch bit
When b1 of EG (Note) is "0": reverse level on INT1 pin When b1 of EG (Note) is "1": level on INT1 pin
?
!
2 P32/CNTR0 latch bit When b2 of EG (Note) is "0":
reverse level on CNTR0 pin When b2 of EG (Note) is "1": level on CNTR0 pin
?
!
3 P33/CNTR1 latch bit When b3 of EG (Note) is "0":
reverse level on CNTR1 pin When b3 of EG (Note) is "1": level on CNTR1 pin
?
!
4 Nothing is allocated for these bits. These to are write disabled bits and are undefined at 7 reading. Note: EG is the Edge polarity selection register.
?
?!
Fig. 1.12.16 Structure of Input latch register
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(7) Edge polarity selection register (EG: Address 00D416) The Edge polarity selection register consists of bits that control a polarity selection of each of the INT0, INT1, CNTR0 and CNTR1 pins and an INT1 interrupt or key on wake-up interrupt selection at stop mode or wait mode. Figure 1.12.17 shows a structure of Edge polarity selection register.
Edge polarity selection register
b7 b6 b5 b4 b3 b2 b1 b0
Edge polarity selection register (EG) [Address 00D416] Name 0 INT0 edge selection bit B 1 INT1 edge selection bit 2 CNTR0 edge selection bit 3 CNTR1 edge selection bit 4 CNTR0/CNTR1 interrupt selection bit Function 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : CNTR0 1 : CNTR1
At reset
RW
0 0 0 0 0
5 INT1 source selection 0 : P31/INT1 bit (at STP or WIT 1 : P00 to P07 "L" level input instruction execution) (for key-on wake-up) 6, 7 Nothing is allocated for these bits. These are write disabled bits and are undefined at reading.
0
?
?!
Fig. 1.12.17 Structure of Edge polarity selection register
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1.13 Serial I/O
The 7470/7471/7477/7478 group can transmit or receive 8-bit data in series by Serial I/O. The Serial I/O transmit/receive method is shown below. q In the 7470/7471 group, only the clock synchronous is available. q In the 7477/7478 group, either clock synchronous or clock asynchronous (UART) can be selected. There are differences in circuit configuration and applicable registers between them. This section explains each of them as "1.13A 7470/7471 group part" and "1.13B 7477/7478 group part." Table 1.13.1 shows defferences between 7470/7471 group and 7477/7478 group. Table 1.13.1 7470/7471 group vs. 7477/7478 group serial I/O 7470/7471 group Serial I/O transmit/ Clock synchronous receive method Clock asynchronous
SRDY signal output
V1 V1 V2
7477/7478 group
SARDY signal output
Byte specification mode
V1 SRDY and SARDY signal : Signal that indicates a Serial I/O transfer ready state V2 Byte specification mode : Mode for transmitting or receiving 1-byte data of a specific cycle out of
multiple-byte data to be transmitted or received.
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1.13A 7470/7471 group part
1.13A.1 Operation description The 7470/7471 group incorporates a clock synchronous Serial I/O. The 8 shift clocks obtained by the clock control circuit are used as synchronous clocks for transmitting or receiving data. The transmit operation of the transmit side and the receive operation of the receive side are simultaneously executed in synchronization with these shift clocks. q The transmit side transmits data bit by bit from the P15/SOUT pin in synchronization with the fall of each shift clock. q The receive side receives data bit by bit from the P14/SIN pin in synchronization with the rise of each shift clock. Figure 1.13A.1 shows a Serial I/O block diagram.
XCIN
1/2
XIN
1/2
1/4
Counter 1/2 1/4 1/64 SM1 SM0
CM7
SARDY
SRDY CLK input SM5 SRDY Synchronous circuit SM2
(Address 00DE16) CLK output Serial I/O counter (3) Serial I/O interrupt request SM6 Byte counter (4)
(Address 00DE16)
Data bus
(Address 00DD16) SIN SOUT
Q S R
Serial I/O register (8)
V: The 7470 group is not provided with the XCIN pin.
Fig. 1.13A.1 Serial I/O block diagram
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2 Communication format The half-duplex data communication or the full-duplex data communication are available. 2 Synchronous clock The internal clock or the external clock can be selected as a synchronous clock by bit 2 of the Serial I/O mode register (SM: address 00DC16). q The synchronous clock for the case where the internal clock is selected is shown below. * f(XIN)/8 * f(XIN)/16 * f(XIN)/32 * f(XIN)/512 * f(XCIN)/8 * f(XCIN)/16 * f(XCIN)/32 * f(XCIN)/512

When the system clock is f(XIN)
When the system clock is f(XCIN)
Notes 1: In the 7470 group, f(XCIN) is not available. 2: When selecting a divided signal of f(XCIN), set the system clock to the low-speed mode by bit 7 of the CPU mode register. q When the external clock is selected, the synchronous clock is an external clock input from the P16/ CLK pin. Notes on external clock selection q When writing data into the Serial I/O register, perform a write operation while the synchronous clock is at "H." q The shift operation of the Serial I/O register is continued while the synchronous clock is input to the Serial I/O circuit. When the external clock is selected, stop the synchronous clock at the end of 8 cycles. (When the internal clock is selected, the synchronous clock stops automatically.) q Set the "H" and "L" widths (TWH, TWL) of the pulse used as the external clock source to TWH, TWL [s] > 2/(system clock frequency [Hz]). For example, when the system clock is 8 MHz, use a clock of 2 MHz or less (duty ratio 50 %). 2 Shift clock Usually, when a clock synchronous transfer is performed between 2 microcomputers, one microcomputer selects the internal clock and outputs the 8 shift clock pulses generated by a start of transfer operation from the P16/CLK pin. The other microcomputer selects the external clock and uses the clock input from the CLK pin as a synchronous clock. 2 SRDY signal, SARDY signal A Serial I/O transfer ready status can be known to the outside by outputting the SRDY signal and the SARDY signal.
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2 Transmit operation of Serial I/O The transmit operation of the Serial I/O is described below. q Start of transmit operation V2 Transmit operation begins by writing transmit data into the Serial I/O register in the transmit V1 enable state. At the time when this data has been written, "7" is set in the Serial I/O counter (address 00DE16, bit 4 - 6), so that the synchronous clock is forced to go to "H."
V 1: State in which the register for transmit operation has been initialized. Refer to "[Transmit
setting method]" which will be described later.
V 2: When the external clock is selected, perform a write operation while the synchronous clock is
at "H." q Transmit operation 1The transmit data written in the Serial I/O register is output from the P15/SOUT pin in synchronization with the fall of the synchronous clock. At this time, the Serial I/O counter is decremented by 1. 2Transmit data is output starting with the least significant bit of the Serial I/O register. Each time one bit is output, the contents of the Serial I/O register are shifted by 1 in the direction of the least significant bit. 3After the transmit shift operation is completed, an interrupt request occurs at the rise of the last V3 cycle of the synchronous clock, so that the Serial I/O interrupt request bit is set to "1."
V 3: When the internal clock is selected as a synchronous clock, the shift clock supply to the Serial
I/O register is automatically stopped after 8-bit data is transmitted (the Serial I/O counter overflows). When the external clock is selected, the contents of the Serial I/O register are continuously sifted while the synchronous clock is input. Accordingly, stop it externally. q When using the SRDY output At the time when transmit data has been written, the level of the SRDY signal changes from "H" to "L" and the level of the SARDY signal changes from "L" to "H," by which a receive ready state can be known externally. The SRDY signal goes to "H" at the first fall of the synchronous clock and the SARDY signal goes to "L" at the rise of the last cycle of the synchronous clock. Figure 1.13A.2 shows a transmit operation and Figure 1.13A.3 shows a transmit timing chart.
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1
Data bus
Synchronous clock
Address 00DD16
Write transmit data
Serial I/O register
b0 D7 D6 D5 D4 D3 D2 D1 Serial I/O register
D0 P15/SOUT
2 Synchronous clock
b0 D7 D6 D5 D4 D3 Transmit shift register D2 P15/SOUT
3 Synchronous clock
b0 D7 Interrupt request register 1 (Address 00FC16) 0 by rising edge 1 b6
Fig. 1.13A.2 Serial I/O transmit operation
Synchronous clock, internal clock divided by 8 to 512, or external clock
SOUT pin
D0
D1
D2
D3
D4
D5
D6
D7
Write signal to serial I/O register
SRDY signal
SARDY signal
Serial I/O interrupt enable bit
Serial I/O interrupt request bit
A A:Clearing by writing "0" to the Serial I/O interrupt request bit. *
* Clearing by accepting the Serial I/O interrupt.
Fig. 1.13A.3 Serial I/O transmit timing chart
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[Transmit setting method] 1Clear the Serial I/O interrupt enable bit (bit 6 of the Interrupt control register 1) to "0." 2Set the Serial I/O mode register according to "Table 1.13A.1." 3When using the Serial I/O interrupt, [1] Clear the Serial I/O interrupt request bit (bit 6 of the Interrupt request register 1) to "0." [2] Set the Serial I/O interrupt enable bit to "1." 4Write transmit data into the Serial I/O register (address 00DD16). Note: When the external clock is selected, perform a write operation while the synchronous clock is at "H." Table 1.13A.1 shows a Serial I/O transmit setting. Table 1.13A.1 Serial I/O transmit setting Register to be used Item f(XIN)/8 f(XCIN)/8 f(XIN)/16 f(XCIN)/16 f(XIN)/32 f(XCIN)/32 f(XIN)/512 f(XCIN)/512 External clock Internal clock Serial I/O port (SOUT, CLK) (Note 2) Ordinary port SRDY signal output SRDY signal SARDY signal Ordinary mode Byte specification mode CMOS output N channel open drain output Serial I/O mode register (SM: Address 00DC16) Bit Setting value 00 01 b1 * b0 10 11 b2 b3 b4 b5 b6 b7 0 1 1 0 1 0 1 0 1 0 1
Synchronous clock (at internal clock selection) (Note 1)
Synchronous clock selection Serial I/O port using
SRDY signal output selection SRDY signal selection
Serial I/O Byte specification mode selection P15/SOUT, SRDY pin output format (Note 3)
Notes 1: Select the internal clock as a synchronous clock in the following condition. In the 7470 group, however, f(XCIN) is not available. q When a divided signal of f(XIN) is selected, the system clock is f(XIN). q When a divided signal of f(XCIN) is selected, the system clock is f(XCIN). Select a system clock state by bit 7 of the CPU mode register. 2: When the ordinary port is switched over to the Serial I/O port, the Serial I/O interrupt request bit may be set to "1." Clear the Serial I/O interrupt request bit to "0" after one instruction or more after switching the ordinary port over to the Serial I/O port. 3: When ordinary P17 is selected by bit 4 of the Serial I/O mode register, the CMOS output is provided regardless of the set value of bit 7.
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2 Receive operation of Serial I/O The receive operation of the Serial I/O is described below. q Start of receive operation Receive operation begins by writing the following data into the Serial I/O register (SIO: address 00DD16) V2 in the receive enable state.V1 * Transmit data in the full-duplex data communication * Arbitrary dummy data in the half-duplex data communication At the time when this data has been written, "7" is set in the Serial I/O counter (address 00DE16, bit 4 - 6), so that the synchronous clock is forced to go to "H."
V 1: State in which the register for receive operation has been initialized. Refer to "[Receive setting
method]" which will be described later. V 2: When the external clock is selected, perform a write operation while the synchronous clock is at "H." q Receive operation 1Receive data is input from the P14/SIN pin to the Serial I/O register in synchronization with the rise of the synchronous clock. At this time, the Serial I/O counter is decremented by 1. 2Receive data is input starting into the most significant bit of the Serial I/O register. Each time one bit is input, the contents of the Serial I/O register are shifted by 1 in the direction of the least significant bit. 3After the receive shift operation is completed, an interrupt request occurs at the rise of the last cycle of the synchronous clock, so that the Serial I/O interrupt request bit is set to "1".V3
V3: When the internal clock is selected as a synchronous clock, the shift clock supply to the Serial
I/O register is automatically stopped after 8-bit data is transmitted (the Serial I/O counter overflows). When the external clock is selected, the contents of the Serial I/O register are continuously sifted while the synchronous clock is input. Accordingly, stop it externally. q When using the SRDY output At the time when data has been written into the Serial I/O register, the level of the SRDY signal changes from "H" to "L" and the level of the SARDY signal changes from "L" to "H," by which a receive ready state can be known externally. The SRDY signal goes to "H" at the first fall of the synchronous clock and the SARDY signal goes to "L" at the rise of the last cycle of the synchronous clock. Figure 1.13A.4 shows a receive operation and Figure 1.13A.5 shows a receive timing chart.
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1
Synchronous clock b0 D0 Serial I/O register Synchronous clock b0 D3 D2 D1 D0
3
Serial I/O register
Synchronous clock D7 D6 D5 D4 D3 D2 D1 D0 0 by rising edge 1 b6
P14/SIN
2
Interrupt request register 1 (Address 00FC16)
P14/SIN
Serial I/O register
Fig. 1.13A.4 Serial I/O receive operation
Synchronous clock, internal clock divided by 8 to 512, or external clock SIN pin
Writing data to Serial I/O register
D0
D1
D2
D3
D4
D5
D6
D7
Reading into Serial I/O register
SRDY signal
SARDY signal
Serial I/O interrupt enable bit
Serial I/O interrupt request bit
A A:Clearing by writing "0" to the Serial I/O interrupt request bit. *
* Clearing by accepting the Serial I/O interrupt.
Fig. 1.13A.5 Serial I/O receive timing chart
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[Receive setting method] 1Clear the Serial I/O interrupt enable bit (bit 6 of the Interrupt control register 1) to "0." 2Clear the Port P14 direction register to "0" to set it to the input mode. 3Clear the Serial I/O mode register according to "Table 1.13A.2." 4When using the Serial I/O interrupt, [1] Clear the Serial I/O interrupt request bit (bit 6 of the Interrupt request register 1) to "0." [2] Set the Serial I/O interrupt enable bit to "1." 5Write the following data into the Serial I/O register. * Transmit data in the full-duplex data communication * Arbitrary dummy data in the half-duplex data communication Note: When the external clock is selected, write data into the Serial I/O register while the synchronous clock is at "H." Table 1.13A.2 shows a Serial I/O receive setting. Table 1.13A.2 Serial I/O receive setting Register to be used Item f(XIN)/8 f(XCIN)/8 f(XIN)/16 f(XCIN)/16 f(XIN)/32 f(XCIN)/32 f(XIN)/512 f(XCIN)/512 External clock Internal clock Ordinary port (P15, P16) (Note 2) Serial I/O port (SOUT, CLK) (Note 3) Ordinary port SRDY signal output SRDY signal SARDY signal Ordinary mode Byte specification mode CMOS output N channel open drain output Serial I/O mode register (SM: Address 00DC16) Bit Setting value 00 01 b1 * b0 10 11 b2 b3 b4 b5 b6 b7 0 1 0 1 0 1 0 1 0 1 0 1
Synchronous clock (at internal clock selection) (Note 1)
Synchronous clock selection Serial I/O port using
SRDY signal output selection SRDY signal selection
Serial I/O Byte specification mode selection P15/SOUT, SRDY pin output format (Note 4, Note 5)
Notes 1: Select the internal clock as a synchronous clock in the following condition. In the 7470 group, however, f(XCIN) is not available. q When a divided signal of f(XIN) is selected, the system clock is f(XIN). q When a divided signal of f(XCIN) is selected, the system clock is f(XCIN). Select a system clock state by bit 7 of the CPU mode register. 2: When the external clock is selected, the P16/CLK pin becomes clock input pin CLK regardless of the set value of bit 3 of the Serial I/O mode register. For this reason, only P15 is available as an ordinary port. 3: When the ordinary port is switched over to the Serial I/O port, the Serial I/O interrupt request bit may be set to "1." Clear the Serial I/O interrupt request bit to "0" after one instruction or more after switching the ordinary port over to the Serial I/O port. 4: When ordinary P17 is selected by bit 4 of the Serial I/O mode register, the CMOS output is provided regardless of the set value of bit 7. 5: When SOUT is selected by bit 3 of the Serial I/O mode register, the data written in the Serial I/O register is output from the SOUT pin in synchronization with the fall of the synchronous clock.
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1.13A.2 Byte specification mode The Serial I/O of the 7470/7471 group has the byte specification mode. This mode permits transmitting or receiving specific one-byte data out of multiple-byte data transmitted or received through the Serial I/O bus. 2 Byte counter (Address 00DE16) The Byte counter is located at the same address as that of the Serial I/O counter but the Serial I/O counter is a read-only type. So this counter is not affected by any write operation to the Byte counter. Because the Byte counter is not provided with a reload function, re-set a value to transmit or receive data continuously. 2 SARDY When the SARDY signal is selected in the byte specification mode, the N channel open drain is selected as its output type, and the SRDY pins of multiple microcomputers are connected, the SARDY signal goes to "H" only when all the microcomputers have become ready for data transfer. 2 Operations in the byte specification mode After setting the Serial I/O mode register, specify a byte corresponding to the clock to be used for a Serial I/O transmit/receive in the Byte counter. Where the value written in the Byte counter is n, a Serial I/O transmit/receive is performed by the clock of the (n + 1)-th byte. q Start of transmit/receive operation A transfer operation is started by writing the data (arbitrary dummy data in the half-duplex data V1 communication) to be transmitted to the Serial I/O register.
V1: When the external clock is selected, write data into the Serial I/O register when the synchronous
clock is at "H." However, if the Byte counter value is a value other than "0," writing data is enabled even if the synchronous clock is at "L." q Transmit/receive operation 1Each time the synchronous clock is input in 8 cycles, the Byte counter value is decremented by 1. 2With the synchronous clock of the next 8 cycles after the Byte counter value becomes "0," a V2 Serial I/O transmit/receive is performed as in the ordinary mode. After completion of the 8-bit data output, an interrupt occurs at the rise of the last cycle of the synchronous clock, so that bit 6 of the Interrupt request register (address 00FC16) is set to "1." 3When the Byte counter overflows, the Serial I/O transfer stops.
V 2: When the Byte counter value is a value other than 0, the output of the SOUT pin goes to "H"
at the fall of the first synchronous clock. If the N channel open drain is selected as the output type of the SOUT pin, the output is put into a high-impedance state, so the SOUT pin can be connected to the SOUT pin of another microcomputer.
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Figure 1.13A.6 shows a transmit/receive operation in the byte specification mode.
1
Byte counter
n16 (n-1)16 0
2 When transmit
Synchronous clock b0 D7 D6 D5 D4 D3 D2 D1 D0 P15/SOUT P14/SIN
When receive
Synchronous clock b0 D0
Serial I/O register
Synchronous clock 8 cycles b0 D7
Serial I/O register
Synchronous clock D7 D6 D5 D4 D3 D2 D1D0
Interrupt request register 1 (Address 00FC16)
0 by rising edge 1 b6
3
Byte counter
FF16
Fig. 1.13A.6 Transmit/receive operation in byte specification mode
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[Byte specification mode setting] For a Serial I/O transfer in the byte specification mode, refer to the setting method in the ordinary mode in "1.13A.1 Operation description," and also take the following into consideration. q Select the byte specification mode. (Set bit 6 of the Serial I/O register to "1.") q Be sure to select the external clock as the synchronous clock. (Clear bit 2 of the Serial I/O mode register to "0.") [1] When data is received, the ordinary port can be selected by the Serial I/O port selection bit (bit 3 of the Serial I/O mode register). P16 pin is used as a external clock input pin CLK. Only P15 is available as an ordinary port. [2] Write data into the Serial I/O register when the synchronous clock is at "H." However, if the Byte counter value is a value other than "0," writing data is enabled even if the synchronous clock is at "L." q When performing a Serial I/O transmit/receive at the n-th byte, write (n - 1) in the Byte counter. Note: Because the Byte counter is not provided with a reload function, re-set a value to transmit or receive data continuously.
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1.13 Serial I/O
1.13A.3 Pins The 7470/7471 group uses 4 pins for data transmit, data receive, shift clock transmit/receive and receive ready signal output. All these pins are used in common with P1. A function selection is made by the Serial I/O port selection bit (bit 3) and the SRDY signal output selection bit (bit 4) of the Serial I/O mode register (SM : Address 00DC16). The function of each pin is explained below. (1) Data transmit pin [SOUT] Transmit data is output bit by bit. This pin is used in common with P15. When the Serial I/O port selection bit (bit 3) of the Serial I/O mode register is set to "1," this pin becomes a Serial I/O data output pin. (2) Data receive pin [SIN] Data is input bit by bit. This pin is used in common with P14. When the port P14 direction register is put into the input mode, this pin becomes a Serial I/O data input pin. (3) Shift clock transmit/receive pin [CLK] This pin inputs (receives from the outside) or outputs (supplies to the outside) the shift clock for data transmit/receive. This pin is used in common with P16. The internal clock or the external clock can be selected by bit 2 of the Serial I/O mode register. (4) Receive enable signal output pins [SRDY], [SARDY] This pin informs the outside of a receive ready state. This pin is used in common with P17. q SRDY signal * SRDY signal output selection bit (bit 4) of Serial I/O mode register is set to "1." * SRDY signal selection bit (bit 5) of Serial I/O mode register is cleared to "0." When the above 2 conditions are satisfied, the level of the pin changes from "H" to "L" at the timing at which data is written into the Serial I/O register, informing the outside of a receive ready state. q SARDY signal * SRDY signal output selection bit (bit 4) of Serial I/O mode register is set to "1." * SRDY signal selection bit (bit 5) of Serial I/O mode register is set to "1." When the above 2 conditions are satisfied, the level of the pin changes from "L" to "H" at the timing at which data is written into the Serial I/O register, informing the outside of a receive ready state. 1.13A.4 Notes on use When the external clock is selected, take the following points into consideration. 1When writing data into the Serial I/O register, perform a write operation while the synchronous clock is at "H." 2The shift operation of the Serial I/O register is continued while the synchronous clock is input to the Serial I/O circuit. When the external clock is selected, stop the synchronous clock at the end of 8 cycles. (When the internal clock is selected, the synchronous clock stops automatically at the end of 8 cycles.) 3Set the "H" and "L" widths (TWH, TWL) of the pulse used as the external clock source to TWH, TWL [s] > 2/(system clock frequency [Hz]). For example, when the system clock is 8 MHz, use a clock of 2 MHz or less (duty ratio 50 %).
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1.13 Serial I/O
1.13A.5 Related registers (1) Serial I/O register (SIO: Address 00DD16) The Serial I/O register is written Serial I/O transmit data or is read receive data. q When transmitting data, write transmit data into this register. q Receive data can be obtained by reading this register. Figure 1.13A.7 shows a structure of the Serial I/O register.
Serial I/O register (7470/7471 group)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O register (SIO) [Address 00DD16] B Function
At reset
RW
0 At transmit: A value of "0016" to "FF16" can be to set as transmit data. 7 At the transmit, data is transmitted one bit at a time starting with the least significant bit. At receive: At the receive, data is received one bit at a time starting with the most significant bit.
?
Fig. 1.13A.7 Structure of Serial I/O register
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(2) Serial I/O counter, Byte counter (Address 00DE16) The Serial I/O counter and the Byte counter are located at the same address. q Serial I/O counter (bit 4 - bit 6) The Serial I/O counter is set to "7" by writing transmit data into the Serial I/O register and counts the synchronous clock of the Serial I/O eight times. The Serial I/O counter is a read-only type and not affected by any write operation to the Byte counter. q Byte counter (bit 0 - bit 3) In the Serial I/O byte specification mode, the value written in the Byte counter is counted down at 8 cycles of the synchronous clock. When the value becomes "0," a Serial I/O transmit/receive is performed by the synchronous clock of the next 8 cycles. Because a reload function is not available, re-set a value to transfer data continuously in the byte specification mode. Figure 1.13A.8 shows a structure of the Serial I/O counter and the Byte counter.
Serial I/O counter and Byte counter (7470/7471 group)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O counter and Byte counter [Address 00DE16] B Function 0 Byte counter to When using the byte specification mode, set 3 a value of "0016" to "0F16." Supposing that the value to be written into the byte counter is "n," a Serial I/O transmit/receive is performed with the clock of the "n + 1"-th byte. 4 Serial I/O counter to When the internal clock is selected as a 6 synchronous clock, this counter generates 8 shift clocks. When transmit data is written into the Serial I/O register, "07 16" is set in the Serial I/O counter. 7 Nothing is allocated for this bit. This is write disabled bit and is undefined at reading.
At reset
RW
?
?
!
?
?!
Fig. 1.13A.8 Structure of Serial I/O counter and Byte counter
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1.13 Serial I/O
(3) Serial I/O mode register (SM: Address 00DC16) The Serial I/O mode register selects a state of the clock or port to be used for a data transfer. Figure 1.13A.9 shows a structure of the Serial I/O mode register.
Serial I/O mode register (7470/7471 group)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O mode register (SM) [Address 00DC16] B Name
b1 b0
Function
0 0 1 1 0 : f(XIN)/8 or f(XCIN)/8 1 : f(XIN)/16 or f(XCIN)/16 0 : f(XIN)/32 or f(XCIN)/32 1 : f(XIN)/512 or f(XCIN)/512 (Note)
At reset
RW
0, 1 Internal clock selection bits
0
2 3
Synchronous clock 0 : External clock selection bit 1 : Internal clock Serial I/O port selection bit SRDY signal output selection bit SRDY signal selection bit Serial I/O byte specify mode selection bit 0 : Ordinary I/O port (P15, P16) 1 : Serial I/O port (SOUT, CLK pin) 0 : Ordinary I/O port(P1 7) 1 : SRDY signal output pin 0 : SRDY signal 1 : SARDY signal 0 : Ordinary mode 1 : Byte specify mode
0 0 0 0 0 0
4 5 6 7
P15/SOUT, SRDY output 0 : CMOS output structure selection bit 1 : N-channel open-drain output
Note: Since the 7470 group is not provided with the sub-clock generating circuit, do not select f(XCIN).
Fig. 1.13A.9 Structure of Serial I/O mode register
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1.13B 7477/7478 group part
1.13B.1 Operation description The 7477/7478 group incorporates a Serial I/O that permits selecting one of the clock synchronous and the clock asynchronous. This section describes the operation in each of the clock synchronous serial I/ O and the clock asynchronous Serial I/O (UART). (1) Clock synchronous Serial I/O In the clock synchronous Serial I/O, the 8 shift clocks obtained by the clock control circuit are used as synchronous clocks for transmitting or receiving. The transmit operation of the transmit side and the receive operation of the receive side are simultaneously executed in synchronization with these shift clocks. q The transmit side transmits data bit by bit from the P15/TxD pin in synchronization with the fall of each shift clock. q The receive side receives data bit by bit from the P14/RxD pin in synchronization with the rise of each shift clock. Figure 1.13B.1 shows a clock synchronous Serial I/O block diagram.
Data bus
P16 RXD
P14
Address 00E016
Serial I/O control register Address 00E216 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit
Receive buffer register
Receive enable bit (RE)
Receive shift register Shift clock
SCLK XCIN XIN SRDY
V
Serial I/O enable bit (SIOE)
BRG count source selection bit (CSS)
Serial I/O synchronous clock selection bit (SCS) Dividing ratio 1/(n+1)
1/4
SRDY output enable bit (SRDY)
Baud rate generator
1/4
Address 00E416
1/4
F/F
Falling detected
Transmit enable bit (TE)
Shift clock
Clock control circuit Transmit shift completion flag (TSC) Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 00E116
TXD P15
Transmit shift register
Transmit interrupt source selection bit (TIC)
P17
Transmit buffer register
Address 00E016 Data bus
V: The 7477 group is not provided with the XCIN pin.
Fig. 1.13B.1 Clock synchronous Serial I/O block diagram
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2 Communication format The half-duplex data communication or the full-duplex data communication are available for communication. 2 Synchronous clock The following can be selected as a synchronous clock by bit 1 of the Serial I/O control register (SIOCON: address 00E216). q "0" : Baud rate generator (BRG) output divided by 4 q "1" : External clock input from the SCLK pin The BRG output is set by the baud rate generator (BRG: address 00E416), which is an 8-bit counter dedicated to the Serial I/O. As an input clock to the BRG, f(XIN)/4 or f(XCIN)/4 (at "0"), f(XIN)/16 or f(XCIN)/16 (at "1") can be selected by bit 0 of the Serial I/O control register. Notes on external clock selection q When setting the transmit enable bit to "1" or writing data into the Transmit buffer register, perform a write operation while the synchronous clock is at "H." q The shift operation of the Transmit shift register or the Receive shift register is continued while the synchronous clock is input to the Serial I/O circuit. When the external clock is selected, stop the synchronous clock at the end of 8 cycles. (When the internal clock is selected, the synchronous clock stops automatically at the end of 8 cycles.) q Set the "H" and "L" widths (TWH, TWL) of the pulse used as the external clock source to TWH, TWL [s] > 8/(system clock [Hz]). For example, when a system clock is 8 MHz, use a clock of 500 kHz or less (duty ratio 50 %). 2 Shift clock Usually, when a clock synchronous transfer is performed between 2 microcomputers, one microcomputer selects the internal clock and outputs the 8 shift clock pulses generated by a start of transmit operation from the P16/SCLK pin. The other microcomputer selects the external clock and uses the clock input from the P16/SCLK pin as a synchronous clock. 2 Data transfer rate (baud rate) In the clock synchronous Serial I/O, the expression for calculating a data transfer rate (baud rate), which is the frequency of the synchronous clock is shown below.
q When the internal clock is selected (using the BRG) Baud rate [bps] =
V1
Division ratio
f(XIN) V2 ! (BRG set value + 1) ! 4
V1 Division ratio : Select "4" or "16" by the BRG count source selection bit. V2 BRG set value : 0 - 255 (0016 - FF16)
q When the external clock is selected Baud rate [bps] = Input clock frequency to SCLK pin
The BRG is an 8-bit counter dedicated to the Serial I/O, having a reload register, and divides the count source by (n + 1) by setting the value n. As a count source, f(XIN)/4 or f(XCIN)/4 (at "0"), f(XIN)/ 16 or f(XCIN)/16 (at "1") can be selected by bit 0 of the Serial I/O control register.
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2 SRDY signal The clock synchronous Serial I/O can inform the outside that a serial transfer has become ready, by outputting the SRDY signal. 2 Transmit operation of the clock synchronous Serial I/O The transmit operation of the clock synchronous Serial I/O is described below. q Start of transmit operation V2 Transmit data is transmitted by writing it into the Transmit buffer register (TB: address 00E016) V1 in the transmit enable state. When the internal clock is selected as a synchronous clock, 8 shift clocks are generated at the time when this set value has been written. q Transmit operation V2 1After transmit data is written into the Transmit buffer register, the transmit buffer empty flag (bit 0) of the Serial I/O status register is cleared to "0." 2The transmit data written in the Transmit buffer register is transferred to the Transmit shift V3 register. 3When the data transfer from the Transmit buffer register to the Transmit shift register is completed, V4 the transmit buffer empty flag is set to "1." 4The transmit data transferred to the Transmit shift register is output from the P15/TxD pin in synchronization with the fall of the synchronous clock. 5When a transmit shift operation is started, the transmit shift completion flag (b2) of the Serial V5 I/O status register is cleared to "0." 6Data is output starting with the least significant bit of the Transmit shift register. Each time onebit data is output, the contents of the Transmit shift register are shifted by 1 bit in the direction of the least significant bit. 7At the time when the transmit shift operation has been completed, the Transmit shift register V3 V5 shift completion flag is set to "1."
V 1: Status in which the register for transmit operation has been completed. Refer to "[Clock
synchronous Serial I/O setting method]" which will be described later.
V 2: When the external clock is selected, write data into the Transmit buffer register when the
synchronous clock is at "H." V 3: A transmit interrupt request occurs immediately after the transfer of 2 when the transmit interrupt source bit (bit 3) of the Serial I/O control register (SIOCON) is "0," or at the time of 7 when the said bit is "1." V 4: While the transmit buffer empty flag is "1," the next transmit data can be written into the Transmit buffer register. V 5: When the internal clock is used as a synchronous clock, the shift clock supply to the Transmit shift register is automatically stopped after 8-bit data is transmitted. However, if the next transmit data is written to the Transmit buffer register while the Transmit shift register shift completion flag is "0," the shift clock supply is continued and serial data is continuously output from the TxD pin.
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q When using the SRDY output At the time when data has been written into the Transmit buffer register, the SRDY pin changes from "H" to "L," informing the outside of a receive ready state. The SRDY pin is restored to "H" at the first fall of the synchronous clock. q Transmit interrupt operation (valid when the Serial I/O is selected) Regarding a transmit interrupt, interrupt request generating timing can be selected by bit 3 of the Serial I/O control register (SIOCON). 0: When the Transmit buffer register becomes empty after the data written in the Transmit buffer register is transferred to the Transmit shift register, an interrupt request is generated. 1: When the shift operation of the Transmit shift register is completed, an interrupt request is generated. Figure 1.13B.2 shows a transmit operation of clock synchronous Serial I/O and Figure 1.13B.3 shows a transmit timing chart of clock synchronous Serial I/O.
1
Data bus Address 00E016 Transmit data writing
5
Serial I/O status register (Address 00E116)
1 0 b2
Transmit buffer register Serial I/O status register (Address 00E116)
b0 1 0
6
Synchronous clock b0 D7 D6 D5 D4 D3 D2
Transmit shift register
2
D1 P15/TxD
Transmit buffer register Transmit data transfer Transmit shift register
7 3
Serial I/O status register (Address 00E116)
Synchronous clock b0 D7
Transmit shift register
0 1 b0
P15/TxD
V When "0" is selected by the bit 3 of the Serial I/O control register 0 Interrupt request register 1
(Address 00FC16)
Serial I/O status register (Address 00E116)
0
1 b6
4
Synchronous clock b0 D7 D6 D5 D4 D3 D2 D1
Transmit shift register
1 b2 V When "1" is selected by the bit 3 of the Serial I/O control register D0 P15/TxD
Interrupt request register 1 (Address 00FC16)
0 1 b6
Fig. 1.13B.2 Transmit operation of clock synchronous Serial I/O
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Synchronous clock, BRG divided by 4, or external clock
TXD pin
D0
D1
D2
D3
D4
D5
D6
D7
Write signal to transmit buffer register
SRDY pin
Transmit buffer empty flag Transmit shift completion flag
B1 B2
Transmit interrupt enable bit
Transmit interrupt request bit
B1
A1
B2
A2
A1
A2 : * Clearing by writing "0" to the transmit interrupt request bit.
* Clearing by accepting the transmit interrupt.
B1 : When interrupt request generation is selected, when the Transmit buffer register
becomes empty by clearing the transmit interrupt source selection bit to "0".
B2 : When interrupt request generation is selected, when the shift operation of the
transmit shift register is completed by setting the transmit interrupt source selection bit to "1".
Fig. 1.13B.3 Transmit timing chart of clock synchronous Serial I/O
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1.13 Serial I/O
[Clock synchronous Serial I/O transmit setting method] 1Clear the Serial I/O transmit interrupt enable bit (bit 6 of Interrupt control register 1) to "0." 2When selecting the internal clock, set the BRG value. 3Set the Serial I/O control register according to Table 1.13B.1. 4When using a Serial I/O transmit interrupt [1] Clear the Serial I/O transmit interrupt request bit (bit 6 of Interrupt request register 1) to "0." Note: When the ordinary port is switched over to the Serial I/O port, the Serial I/O transmit interrupt request bit may be set to "1." Clear the Serial I/O transmit interrupt request bit to "0" after one instruction or more after switching the ordinary port over to the Serial I/ O port. [2] Set the Serial I/O transmit interrupt enable bit to "1." 5Write transmit data into the Transmit buffer register (TB: address 00E016). Note: When the external clock is selected, perform a write operation while the synchronous clock is at "H." Table 1.13B.1 Clock synchronous Serial I/O transmit setting Register to be used Item BRG count source selection Synchronous clock selection
SRDY signal output selection
Transmit interrupt request selection Transmit enable selection Receive enable selection Clock synchronous selection Serial I/O enable selection
f(XIN)/4 or f(XCIN)/4 f(XIN)/16 or f(XCIN)/16 BRG output divided by 4 External clock input Ordinary port SRDY signal output Transmit buffer empty When the transmit shift operation is completed Transmit enable Disable (half-duplex data communication) Enable (full-duplex data communication) Clock synchronous P14 to P17 function as serial I/O pins
Serial I/O control register (SIOCON: Address 00E216) Setting value Bit 0 b0 1 0 b1 1 0 b2 1 0 b3 1 1(Note) b4 0 b5 1 1 b6 1 b7
Note: When the external clock is selected, write "1" in bit 4 (transmit enable bit) while the synchronous clock is at "H."
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2 Receive operation of clock synchronous Serial I/O The receive operation of the clock synchronous Serial I/O is described below. q Start of receive operation V2 Receive operation begins by writing data into the Transmit buffer register (TB: address 00E016) V1 in the receive enable state. * Transmit data in the full-duplex data communication * Arbitrary dummy data in the half-duplex data communication q Receive operation 1Receive data is input bit by bit from the P14/RxD pin to the Receive shift register in synchronization with the rise of the synchronous clock. 2Receive data is input starting with the most significant bit of the Receive shift register. Each time one bit is input, the contents of the Receive shift register are shifted by 1 in the direction of the least significant bit. 3After one-byte data is completely input to the Receive shift register, the contents of the Receive V3 shift register are transferred to the receive buffer register (RB). 4When receive data has been transferred to the receive buffer register, the receive buffer full flag V4 (b1) of the Serial I/O status register (SIOSTS) is set to "1," so that a receive interrupt request is generated.
V 1: Status in which the register for receive operation has been completed. Refer to "[Clock
synchronous Serial I/O receive setting method]" which will be described later.
V 2: When the external clock is selected, write data into the Transmit buffer register when the
synchronous clock is at "H." V 3: If receive data is further input to the Receive shift register when data remains (when the receive buffer full flag is "1") without reading out the contents of the Receive buffer register, the overrun error flag of the Serial I/O status register is set to "1." At this time, the data of the Receive shift register is not transferred to the Receive buffer register and the original data of the Receive buffer register is held. V 4: The receive buffer full flag is cleared to "0" by reading out the Receive buffer register. q When using the SRDY output At the time when data has been written into the Transmit buffer register, the level of the SRDY signal changes from "H" to "L" by which a receive ready state can be known externally. The SRDY signal goes to "H" at the first fall of the synchronous clock of the synchronous clock. q Receive interrupt operation (Serial I/O select only) When receive data is transferred from the receive shift register to the Receive buffer register after one-byte data is all input to the Receive shift register, an interrupt request is generated. Figure 1.13B.4 shows a receive operation of the clock synchronous Serial I/O and Figure 1.13B.5 shows a receive timing chart of the clock synchronous Serial I/O.
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1
Synchronous clock
b0 D0 P14/RxD
Receive shift register
Synchronous clock
4
Serial I/O status register (Address 00E116)
0 1 b1 0 1 b5
2
b0 D3 D2 D1 D0 P14/RxD
Receive shift register Interrupt request register 1 (Address 00FC16)
3
Receive shift register
Synchronous clock
D7 D6 D5 D4 D3 D2 D1D0
Receive data transfer (Address 00E016) Receive buffer register
Fig. 1.13B.4 Receive operation of clock synchronous serial I/O
Synchronous clock
RxD pin Writing data to transmit shift register SRDY pin Receive buffer register read signal
D0
D1
D2
D3
D4
D5
D6
D7
Reading into receive shift register
Receive buffer full flag
Receive enable bit
Receive interrupt request bit
A:Clearing by writing "0" to the receive interrupt request bit. *
* Clearing by accepting the receive interrupt.
A
Fig. 1.13B.5 Receive timing chart of clock synchronous serial I/O
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[Clock synchronous Serial I/O receive setting method] 1Clear the Serial I/O receive interrupt enable bit (bit 5 of interrupt control register 1) to "0." 2When selecting the internal clock, set the BRG value. 3Set the Serial I/O control register according to Table 1.13B.2. 4When using a Serial I/O receive interrupt [1] Clear the Serial I/O receive interrupt request bit (bit 5 of interrupt request register 1) to "0." Note: When the ordinary port is switched over to the Serial I/O port, the Serial I/O receive interrupt request bit may be set. Clear the Serial I/O receive interrupt request bit to "0" after one instruction or more after switching the ordinary port over to the Serial I/O port. [2] Set the Serial I/O receive interrupt enable bit to "1." 5Set the following data into the Transmit buffer register (TB). * Transmit data in the full-duplex data communication * Arbitrary dummy data in the half-duplex data communication Note: When the external clock is selected, perform a write operation while the synchronous clock is at "H." Table 1.13B.2 Clock synchronous Serial I/O receive setting Register to be used Item BRG count source selection Synchronous clock selection
SRDY signal output selection
Transmit enable selection Receive enable selection Clock synchronous selection Serial I/O enable selection
f(XIN)/4 or f(XCIN)/4 f(XIN)/16 or f(XCIN)/16 BRG output divided by 4 External clock input Ordinary port SRDY signal output (Note 1) Disable (half-duplex data communication) Enable (full-duplex data communication) Receive enable Clock synchronous P14 to P17 function as Serial I/O pins
Serial I/O control register (SIOCON: Address 00E216) Bit Setting value 0 b0 1 0 b1 1 0 b2 1 0 b4 1(Note 2) b5 1 b6 1 b7 1
Notes 1: When the receive side performs an SRDY output by using an external clock, set the receive enable bit, the SRDY output enable bit, and the transmit enable bit to "1" (transmit enable). 2: When the external clock is selected, write "1" in bit 4 (transmit enable bit) while the synchronous clock is at "H."
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(2) Clock asynchronous Serial I/O In case of the clock asynchronous Serial I/O (UART), the transmit operation of the transmit side and the receive operation of the receive side are simultaneously executed by unifying the baud rate and the transfer data format between both transmit side and receive side. Figure 1.13B.6 shows a UART block diagram.
Data bus P14 RXD
Receive enable bit (RE) Address 00E016 Address 00E216
Serial I/O control register Receive buffer full flag (RBF) Receive interrupt request (RI) UART control register
Address 00E316
ST detected 7 bits 8 bits
OE
Receive buffer register Receive shift register
Character length selection bit (CHAS) PE
FE
SP detected
1/16
Clock control circuit
Serial I/O enable bit(SIOE) BRG count source selection bit (CSS)
SCLK V XCIN XIN
Serial I/O synchronous clock selection bit (SCS) Dividing ratio 1/(n+1)
1/4
Baud rate generator 1/4 ST/SP/PA occur
Address 00E416
1/16 Transmit shift completion flag (TSC) Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 00E116
Transmit enable bit (TE)
TXD P16 P15
Transmit shift register
Transmit interrupt source selection bit (TIC) Address 00E016
Character length selection bit (CHAS)
Transmit buffer register
Data bus V: The 7477 group is not provided with the XCIN pin.
Fig. 1.13B.6 UART block diagram
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2 Synchronous clock The following can be selected as a synchronous clock by bit 1 of the Serial I/O control register (SIOCON: address 00E216). q "0" : Baud rate generator (BRG) output divided by 16 q "1" : External clock input from the SCLK pin divided by 16 The BRG output is set by the baud rate generator (BRG: address 00E416), which is an 8-bit counter dedicated to the Serial I/O. As an input clock to the BRG, f(XIN)/4 or f(XCIN)/4 (at "0"), f(XIN)/16 or f(XCIN)/16 (at "1") can be selected by bit 0 of the Serial I/O control register. Precaution on internal clock selection In the UART, when the internal clock is selected as a synchronous clock, the P16/SCLK pin can be used as port P16. Notes on external clock selection q Set the "H" and "L" widths (TWH, TWL) of the pulse used as the external clock source to TWH, TWL [s] > 2/(f(XIN) [Hz]). For example, when f(XIN) = 8 MHz, use a clock of 2 MHz or less (duty ratio 50 %). 2 Data transfer speed (Baud rate) In the UART, the expression for calculating a data transfer speed (baud rate), which is the frequency of the synchronous clock is shown below.
q When the internal clock is selected (using the BRG) Baud rate [bps] = f(XIN) or f(XCIN) Division ratio
V1
! (BRG set value
V2
+ 1) ! 16
V1 Division ratio : Select "4" or "16" by the BRG count source selection bit. V2 BRG set value : 0 - 255 (0016 - FF16)
q When the external clock is selected Baud rate [bps] = Input clock oscillation frequency to SCLK pin 16
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The BRG is an 8-bit counter dedicated to the Serial I/O, having a reload register, and divides the count source by (n + 1) by setting the value n. As a count source, f(XIN)/4 or f(XCIN)/4 (at "0"), f(XIN)/16 or f(XCIN)/16 (at "1") can be selected by bit 0 of the Serial I/O control register. Table 1.13B.3 shows a baud rate reference value. Table 1.13B.3 Baud rate reference value At f(XIN) = 7.9872 MHz Baud rate [bps] BRG set value Count source 300 600 1200 2400 4800 9600 15600 31200 41600 f(XIN)/16 f(XIN)/16 f(XIN)/16 f(XIN)/16 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 103(6716 ) 51(3316 ) 25(1916 ) 12(0C16) 25(1916 ) 12(0C16) 7(0716 ) 3(0316 ) 2(0216 )
At f(XIN) = 3.9936 MHz BRG set value Count source f(XIN)/16 f(XIN)/16 f(XIN)/16 f(XIN)/4 f(XIN)/4 51(3316 ) 25(1916 ) 12(0C16) 25(1916 ) 12(0C16)
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2 Transmit/receive data format A transmit/receive data format can be selected by the bits of the UART control register (UARTCON). * * * * Start bit (ST) Data bit (DATA) Parity bit (PA) Stop bit (SP) : : : : 1-bit 7-bit or 8-bit Non or 1-bit 1-bit or 2-bit
Figure 1.13B.7 shows a transmit/receive data format, Table 1.13B.4 shows a function of each bit of transmit data, and Figure 1.13B.8 shows all data formats.
q For 1ST-8DATA-1PA-2SP
Next transmit data (at continuous output) MSB D7
Transmit data Data bit (8 bits) ST LSB D0 D1 D6 PA SP SP
ST
D0
D1
Fig. 1.13B.7 UART data format Table 1.13B.4 Each bit function of UART transmit data Name Function Start bit ST The "L" signal for 1 bit is added by the bit indicating a start of data transmission immediately before the transmit data. Data bit DATA This bit indicates the transmit data written in the UART transmit buffer register. The "0" data is an "L" signal and the "1" data is an "H" signal. Parity bit PA This bit is added immediately after the data bit for improvement of data reliability. The contents of this bit change according to the contents of the parity selection bit so that the number of "1"s in the transmit data including the parity bit may always be even or odd. Stop bit SP This bit indicates that data has been transmitted, and is added immediately after the data bit (immediately after the parity bit when the parity is valid). The "H" signal for 1 bit or 2 bits is output.
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q For 7-bit UART mode
ST LSB D0 LSB D0 LSB D0 LSB D0 D1 D2 D3 D4 D5 MSB D6 MSB D6 MSB D6 MSB D6 SP
ST: Start bit Di: Data bit PA: Parity bit SP: Stop bit
ST
D1
D2
D3
D4
D5
SP
SP
ST
D1
D2
D3
D4
D5
PA
SP
ST
D1
D2
D3
D4
D5
PA
SP
SP
q For 8-bit UART mode
ST LSB D0 LSB D0 LSB D0 LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 MSB D7 MSB D7 MSB D7 SP
ST
D1
D2
D3
D4
D5
D6
SP
SP
ST
D1
D2
D3
D4
D5
D6
PA
SP
ST
D1
D2
D3
D4
D5
D6
PA
SP
SP
Fig. 1.13B.8 Transmit/receive format of UART
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2 Transmit operation of UART The Transmit operation of the UART is described below. q Start of Transmit operation Transmit data is transmitted by writing it into the Transmit buffer register (TB: address 00E016) in the Transmit enable state. V1 q Transmit operation 1 After transmit data is written into the Transmit buffer register, the transmit buffer empty flag (bit 0) of the Serial I/O status register is cleared to "0." 2 The transmit data written in the Transmit buffer register is transferred to the Transmit shift register. When the data transfer from the Transmit buffer register to the Transmit shift register is completed, the transmit buffer empty flag is set to "1."V2 When the transmit interrupt source bit (bit 3) of the Serial I/O control register (SIOCON) is "0," the interrupt request bit is set to "1," then a transmit interrupt request occurs. 3 The transmit data transferred to the transmit shift register is output from the P15/TxD pin in synchronization with the fall of the synchronous clock starting with the start bit. The start bit, the parity bit and the stop bit are automatically generated and output according to the contents of setting of the UART control register. 4 When a transmit shift operation is started, the transmit shift completion flag (b2) of the Serial I/O status register is cleared to "0." 5 Data is output starting with the least significant bit of the Transmit shift register. Each time onebit data is output, the contents of the Transmit shift register are shifted by 1 bit in the direction of the least significant bit. 6 After one-half a cycle of the synchronous clock V3 after a start of stop bit transmission, the transmit shift completion flag is set to "1." When the bit 3 of the Serial I/O control register is "1" (transmit shift operation is completed), at the time the interrupt request bit is set to "1" and the Transmit interrupt request occurs.
V1: Status in which the register for transmit operation has been completed. Refer to the "[UART
transmit setting method]" which will be described later.
V2: While the transmit buffer empty flag is "1," the next transmit data can be written into the
Transmit buffer register. V3: In case of two stop bits, the stop bit output period is that of the 2nd bit.
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q Transmit interrupt operation (valid when the Serial I/O is selected) Regarding a transmit interrupt, interrupt request generating timing can be selected by bit 3 of the Serial I/O control register (SIOCON). 0: When the Transmit buffer register becomes empty after the data written in the Transmit buffer register is transferred to the Transmit shift register, an interrupt request is generated. 1: When the shift operation of the Transmit shift register is completed, an interrupt request is generated. * In case of the UART, an interrupt operation is performed in the same way as when the synchronous clock is selected. Figure 1.13B.9 shows a transmit operation of UART and Figure 1.13B.10 shows a transmit timing of UART.
1
Data bus Address 00E016
4
Write transmit data b0 1 0 Serial I/O status register
(Address 00E116)
Transmit buffer register Serial I/O status register
(Address 00E116)
1 0 b2
5
Synchronous clock
2
Transmit buffer register Transfer transmit data Transmit shift register
b0 D7 D6 D5 D4 D3 D2 D1 Transmit shift register
D0 P15/TxD SP P15/TxD
Serial I/O status register
(Address 00E116)
0 1 b0
6
Synchronous clock
When "0" is selected by the bit 3 of the Serial I/O control register 0 Interrupt request register 1
(Address 00FC16)
Serial I/O status register
(Address 00E116)
0 1 b2
3
1 b6
Synchronous clock
When "1" is selected by the bit 3 of the Serial I/O control register Interrupt request register 1 P15/TxD
(Address 00FC16)
b0 D7 D6 D5 D4 D3 D2 D1 D0 Transmit shift register
0 1 b6
ST
Fig. 1.13B.9 Transmit operation of UART
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Synchronous clock, BRG output divided by 16, or external clock divided by 16 TXD pin ST D0 D1 D2 D6 D7 SP
Serial I/O not used
Write signal to Transmit buffer register
Transmit buffer empty flag
Transmit shift completion flag
Transmit interrupt enable bit
Transmit interrupt request bit
B1
A1
B2
A2
A1
A2 : * Clearing by writing "0" to the transmit interrupt request bit.
* Clearing by accepting the transmit interrupt.
B1
: When interrupt request generation is selected, when the Transmit buffer register becomes empty by clearing the transmit interrupt source selection bit to "0". : When interrupt request generation is selected, when the shift operation of the Transmit shift register is completed by setting the transmit interrupt source selection bit to "1".
B2
Fig. 1.13B.10 Transmit timing chart of UART
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[UART transmit setting method] 1 Clear the Serial I/O transmit interrupt enable bit (bit 6 of Interrupt control register 1) to "0." 2 When selecting the internal clock, set the BRG value. 3 Set the Serial I/O control register according to Table 1.13B.5. 4 Set the data format according to Table 1.13B.6. 5 When using a Serial I/O transmit interrupt [1] Clear the Serial I/O transmit interrupt request bit (bit 6 of Interrupt request register 1) to "0." Note: When the ordinary port is switched over to the Serial I/O port, the Serial I/O transmit interrupt request may be set to "1." Clear the Serial I/O transmit interrupt request bit to "0" after one instruction or more after switching the ordinary port over to the Serial I/O port. [2] Set the Serial I/O transmit interrupt enable bit to "1." 6 Write transmit data into the Transmit buffer register.
Table 1.13B.5 UART transmit setting Serial I/O control register (SIOCON: Address 00E216) Item bit setting value f (XIN)/4 or f(XCIN)/4 0 b0 BRG count source selection f (XIN)/16 or f(XCIN)/16 1 BRG output divided by 16 0 b1 Synchronous clock selection External clock input divided by 16 1 (Note 1) b2 SRDY signal output selection 0 Transmit buffer empty b3 Transmit interrupt request selection When the transmit shift operation is completed 1 Transmit enable 1 b4 Transmit enable selection Disable (Half-duplex data communication) 0 b5 Receive enable selection Enable (Full-duplex data communication) 1 Clock asynchronization 0 b6 Clock asynchronous selection P14 to P17 function as Serial I/O pins (Note 2) 1 b7 Serial I/O enable selection Notes 1: When the UART is selected, this bit does not function. 2: When the internal clock is selected, the P16/SCLK pin can be used as port P16. Register to be used Table 1.13B.6 Set value of UART control register UART control register (UARTCON: Address 00E316) Serial I/O data transfer format b3 b2 b1 b0 1ST-8DATA-1SP 0 0 0 - 1ST-7DATA-1SP 0 0 1 1ST-8DATA-1PA-1SP 0 Selection 1 0 1ST-7DATA-1PA-1SP 0 (Note) 1 1 1ST-8DATA-2SP 1 0 0 _ 1ST-7DATA-2SP 1 0 1 1ST-8DATA-1PA-2SP 1 Selection 1 0 1 1ST-7DATA-1PA-2SP (Note) 1 1 Note: 0: Even parity 1: Odd parity
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2 Receive operation of UART The receive operation of UART is described below. q Start of receive operation Set the receive enable bit (bit 5) of the Serial I/O control register (SIOCON) to the enable state ("1") in the receive enable state. V1 With this operation, the start bit is detected and serial data is received. q Receive operation 1 After a fall of the P14 /RxD pin is detected, the level of the P14 /RxD pin is checked after onehalf a cycle of the synchronous clock. If its level is "L," the bit is judged as a start bit. When its level is "H," it is judged that noise is generated, so that the the receive operation is stopped and the UART waits for the start bit. 2 Receive data is input bit by bit from the P14/RxD pin to the Receive shift register in synchronization with the rise of the synchronous clock. 3 Data, immediately after the start bit, is input starting with the most significant bit of the Receive shift register. Each time one bit is received, the contents of the Receive shift register are shifted by 1 bit in the direction of the least significant bit. 4 When the specified number of bits are all input in the Receive shift register, the contents of the Receive shift register are transferred to the Receive buffer register (RB). V2,V3 5 After 1/2 cycle of the shift clock after a start of stop bit reception, the receive buffer full flag (bit 1) of the Serial I/O status register (SIOSTS) is set to "1"V4 and a receive interrupt request is generated. 6 Error flag detection is started concurrently with the occurrence of the receive interrupt request.
V1: Status in which the register for receive operation has been completed. Refer to the "[UART
receive setting method]" which will be described later.
V2: When the data bit length is 7 bits, the contents of the Receive buffer register consist of receive
data of bits 0 to 6 and "0" of bit 7 (MSB). V3: If receive data is further input to the Receive shift register when data remains (when the receive buffer full flag is "1") without reading out the contents of the Receive buffer register, the overrun error flag of the Serial I/O status register is set to "1." At this time, the data of the Receive shift register is not transferred to the Receive buffer register and the original data of the Receive buffer register is held. V4: The receive buffer full flag is cleared to "0" by reading out the Receive buffer register.
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q Receive interrupt operation (valid when the Serial I/O is selected) When receive data is transferred from the Receive shift register to the Receive buffer register after one-byte data is all input to the Receive shift register, an interrupt request is generated. * In case of the UART, an interrupt operation is performed in the same way as when the synchronous clock is selected. Figure 1.13B.11 shows a receive operation of UART and Figure 1.13B.12 shows a receive timing of UART.
1
Synchronous clock
5
Synchronous clock "H" level detected judge as noise "L" level detected judge as start bit
Synchronous clock
RxD (SP)
RxD (noise)
RxD (ST)
Serial I/O status register
(Address 00E116)
0 1 b1
2
b0 D0 P14/RxD Receive shift register
Interrupt request register 1
(Address 00FC16)
0 1 b5
3
Synchronous clock
6
b0 Serial I/O status register
(Address 00E116)
0000 1111 b6 b5 b4 b3
D3 D2 D1 D0 P14/RxD Receive shift register
4
Synchronous clock
Receive shift register D7 D6 D5 D4 D3 D2 D1 D0 Receive data transfer
(Address 00E016) Receive buffer register
b3(OE)="1" when the overrun error occurs. b4(PE)="1" when the parity error occurs. b5(FE)="1" when the framing error occurs. b6(SE)="1" when OE U PE U FE=1.
Fig. 1.13B.11 Receive operation of UART
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Synchronous clock
Receive started by falling of ST RXD pin ST D0
Test that level of ST is "L" D1 D2 D6 PAR SP
Receive buffer register read out signal
Read into Receive shift register
Receive buffer full flag
Receive interrupt request bit
A
Receive enable bit
A : * Clearing by writing "0" to the receive interrupt request bit.
* Clearing by accepting the receive interrupt.
Fig. 1.13B.12 Receive timing chart of UART
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[UART receive setting method] 1 Clear the Serial I/O receive interrupt enable bit (bit 5 of Interrupt control register 1) to "0." 2 When selecting the internal clock, set the BRG value. 3 Set the Serial I/O control register according to Table 1.13B.7. 4 Set the data format according to Table 1.13B.6. 5 When using a Serial I/O receive interrupt [1] Clear the Serial I/O receive interrupt request bit (bit 5 of Interrupt request register 1) to "0." Note: When the ordinary port is switched over to the Serial I/O port, the Serial I/O receive interrupt request may be set to "1." Clear the Serial I/O receive interrupt request bit to "0" after one instruction or more after switching the ordinary port over to the Serial I/O port. [2] Set the Serial I/O receive interrupt enable bit to "1." 6 In the full-duplex data communication, set transmit data in the Transmit buffer register (TB).
Table 1.13B.7 UART receive setting Serial I/O control register (SIOCON: Address 00E216) Item bit setting value f (XIN)/4 or f(XCIN)/4 0 b0 BRG count source selection f (XIN)/16 or f(XCIN)/16 1 BRG output divided by 16 0 b1 Synchronous clock selection External clock input divided by 16 1 (Note 1) b2 SRDY signal output selection 0 Transmit buffer empty b3 Transmit interrupt request selection When the transmit shift operation is completed 1 Disable (Half-duplex data communication) 0 b4 Transmit enable selection Enable (Full-duplex data communication) 1 Receive enable 1 b5 Receive enable selection Clock asynchronous 0 b6 Clock asynchronous selection P14 to P17 function as serial I/O pins (Note 2) 1 b7 Serial I/O enable selection Notes 1: When the UART is selected, this bit does not function. 2: When the internal clock is selected, the P16/SCLK pin can be used as port P16. Register to be used
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1.13B.2 Pins The 7477/7478 group uses 4 pins for data transmit, data receive, shift clock transmit/receive and serial I/O transfer ready signal output. All these pins are used in common with P1. A function selection is made by the serial I/O enable bit (bit 7) and the SRDY output enable bit (bit 2) of the Serial I/O control register. The function of each pin is explained below. (1) Data transmit pin[TxD] Transmit data is output bit by bit. This pin is used in common with P15. When the transfer enable bit and the serial I/O enable bit of the Serial I/O control register is set to "1," this pin becomes a serial I/O data output pin. (2) Data receive pin [RxD] Data is input bit by bit. This pin is used in common with P14. When the receive enable bit and the serial I/O enable bit of serial I/O control register are set to "1," this pin becomes a serial I/O data input pin. (3) Shift clock transmit/receive pin [SCLK] 2 Clock synchronous This pin inputs (receives from the outside) or outputs (supplies to the outside) the synchronous clock for data transmit/receive. When the serial I/O synchronous clock selection bit (bit 1) of the Serial I/O control register is cleared to "0" (use of internal clock), the synchronous clock is output. When the same bit is set to "1" (use of internal clock), the synchronous clock is input from the outside. 2 Clock asynchronous (UART) When the serial I/O synchronous clock selection bit (bit 1) of the Serial I/O control register is set to "1" (use of external clock), the synchronous clock is supplied from the outside. When the same bit is cleared to "0" (use of internal clock), this pin does not function. Note: When the internal clock is selected, SCLK pin can be used as port P16. (4) Serial transfer enable signal output pin [SRDY] This pin informs the outside of a receive enable state in the clock synchronous serial I/O. In case of the UART, this pin does not function. q SRDY signal output enable bit (bit 2) of Serial I/O control register is set to "1." q Transmit enable bit (bit 4) of Serial I/O control register is set to "1." When the above 2 conditions are satisfied, the level of the pin changes from "H" to "L" at the timing at which data was written into the Transmit buffer register, informing the outside of a serial I/O transfer enable state.
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1.13B.3 Notes on use (1) Notes on external clock selection In the 7477/7478 group, either the internal clock or external clock can be selected as the synchronous clock. When the external clock is selected as the synchronous clock, take the following points into consideration. 2 Clock synchronous serial I/O 1 During data transmission, when setting the transmit enable bit to "1" or writing data into the Transmit buffer register, perform a write operation while the synchronous clock is at "H." 2 The transmission or the shift operation of the Receive shift register is continued while the synchronous clock is input to the serial I/O circuit. When the external clock is selected, stop the synchronous clock at the end of 8 cycles. When the internal clock is selected, the synchronous clock stops automatically at the end of 8 cycles. 3 When the external clock is selected, set the "H" and "L" widths (TWH, TWL) of the pulse used as the external clock source to TWH, TWL [s] Q 8/(f(XIN) [Hz]). For example, when f(XIN) is 8 MHz, use a clock of 500 kHz or less (duty ratio 50 %). 2 UART Set the "H" and "L" widths (TWH, TWL) of the pulse used as the external clock source to TWH, TWL [s] Q 2/(f(XIN) [Hz]). For example, when f(XIN) is 8 MHz, use a clock of 2 MHz or less (duty ratio 50 %). (2) When the SRDY output is performed in the clock synchronous serial I/O When the receive side using the external clock performs an SRDY output, set the receive enable bit, the SRDY output enable and the transmit enable bit to "1" (transmit enable). (3) When a serial I/O transmit interrupt or a serial I/O receive interrupt is caused 2 When using a serial I/O transmit interrupt 1 Clear the serial I/O transmit interrupt request bit (bit 6 of IR1) to "0" after one instruction or more after setting a value in the Serial I/O control register. 2 After setting in 1, set the serial I/O transmit interrupt enable bit (bit 6 of IE1) to "1." 2 When using a serial I/O receive interrupt 1 Clear the serial I/O receive interrupt request bit (bit 5 of IR1) to "0" after one instruction or more after setting a value in the Serial I/O control register. 2 After setting in 1, set the serial I/O receive interrupt enable bit (bit 5 of IE1) to "1." (4) Transmit interrupt request in the transmit enable state After the transmit enable bit is set to "1," the transmit buffer empty flag and the transmit shift completion flag are set to "1." Accordingly, even if a transmit buffer empty state is selected or a termination of shift operation of the Transmit shift register is selected as a transmit interrupt source, an interrupt request is generated and the transmit interrupt request bit is set to "1." For this reason, when using a transmit interrupt, set the transmit enable bit to "1," clear the transmit interrupt request bit to "0," and then set the transmit interrupt enable bit to "1" (enable state).
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(5) Disabling transmission after transmission of 1-byte data In the 7477/7478 group, it is possible to make reference to the transmit shift register completion flag (TSC flag) to know that data has been transmitted. The TSC flag is "0" during data transmission, and becomes "1" after data has been transmitted. Accordingly, if data transmission is disabled at the time of confirmation of a change of the TSC flag from "0" to "1," data transmission can be terminated after 1-byte data is transmitted. However, the TSC flag is also set to "1" when the serial I/O is enabled and does not become "0" until a synchronous clock is generated and transmitted. For this reason, if data transmission is disabled by making reference to the TSC flag at this time, data is not transmitted. Make reference to the TSC flag after a start of data transmission. The change of the TSC flag from "1" to "0" has a delay of 0.5 to 1.5 cycles of the synchronous clock. (6) Re-setting the Serial I/O control register (SIOCON) Re-set the Serial I/O control register after setting both transmit enable bit and receive enable bit to "0" to re-set the transmit circuit and the receive circuit. 1 Clear both transmit enable bit (TE) and receive enable bit (RE) to "0." 2 Set the bit 0 to bit 3 and bit 6 of the Serial I/O control register. 3 Set both transmit enable bit (TE) and receive enable bit (RE) to "1." (It is possible to set 2 and 3 simultaneously with the LDM instruction.) (7) Stopping data transmit/receive 2 In the following cases, clear the transmit enable bit to "0" (transmit disable). q To stop the transmit operation when data is transmitted in the clock synchronous serial I/O q To stop the transmit operation when UART data is transmitted q To stop only the transmit operation when UART data is transferred 2 In the following cases, clear receive enable bit (receive disable) or serial I/O enable bit to "0" (serial I/O disable). q To stop the receive operation when data is received in the clock synchronous serial I/O 2 In the following cases, clear the receive enable bit to "0." q To stop the receive operation when UART data is received. q To stop only the receive operation when UART data is transferred. 2 In the following cases, clear both transmit enable bit and receive enable bit to "0" (transfer disable) simultaneously. q To stop the transmit operation and the receive operation when data is transferred in the clock synchronous serial I/O Note: When data is transferred in the clock synchronous serial I/O, it is impossible to stop only the transmit operation or the receive operation.
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(8) Processing upon occurrence of errors 2 When a parity error, a framing error or a summing error occurs When a parity error, a framing error or a summing error occurs, the flag corresponding to each error in the Serial I/O status register is set to "1." These flags are not cleared to "0" automatically. Clear them to "0" by software. The parity error flag, the framing error flag and the summing error flag can be cleared to "0" by one of the following two methods. q Clear the receive enable bit to "0." q Write arbitrary dummy data into the Serial I/O status register. 2 Processing upon occurrence of overrun error An overrun error occurs when data has all been input to the Receive shift register while data is stored in the Receive buffer register. When an overrun error occurs, the data of the Receive shift register is not transferred to the Receive buffer register and the data of the Receive buffer register is held. At this time, even if the data of the Receive buffer register is read out, the data of the Receive shift register is not transferred. Accordingly, the data of the Receive buffer register can be read out but the data of the Receive shift register cannot be read out and becomes invalid. When an overrun error occurs, clear the overrun error flag of the Serial I/O status register to "0" and then make preparations for receiving data again. The overrun error flag can be cleared by one of the following methods. q Clear the serial I/O enable bit to "0." q Clear the receive enable bit to "0." q Write arbitrary dummy data into the Serial I/O status register.
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1.13B.4 Related registers (1) Transmit/receive buffer register (TB/RB: Address 00E0 16) The Transmit/receive buffer register is written serial I/O (used in common with the clock synchronous serial I/O and the UART) transmit data and is read out serial I/O receive data. q To transmit data, write this transmit data into this register. q Receive data can be obtained by reading this register. Figure 1.13B.13 shows a structure of the Transmit/receive buffer register.
Transmit/receive buffer register (7477/7478 group)
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/receive buffer register (TB/RB) [Address 00E016] Function A value of "0016" to "FF16" can be 0 At transmit: set as transmit data. to The transmit data is transferred 7 automatically by writing the transmit data into the Transmit shift register. At receive: When all receive data has been input into the Receive shift register, the receive data is automatically transferred to the receive buffer register. B
At reset
RW
?
Fig. 1.13B.13 Structure of Transmit/receive buffer register
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(2) Serial I/O status register (SIOSTS: Address 00E116) The Serial I/O status register consists of flags for representing the buffer/register state to be used for data transfer, and error flags. q This register is a read-only type. q Bit 7 is unused and "1" at a read operation. Figure 1.13B.14 shows a structure of the Serial I/O status register.
Serial I/O status register (7477/7478 group)
b7 b6 b5 b4 b3 b2 b1 b0
1
Serial I/O status register (SIOSTS) [Address 00E116] B 0 1 2 3 4 5 6 7 Name Transmit buffer empty flag (TBE) Receive buffer full flag (RBF) Transmit shift completion flag (TSC) Overrun error flag (OE) Parity error flag (PE) Framing error flag (FE) Summing error flag (SE) Function 0 : Buffer full 1 : Buffer empty 0 : Buffer empty 1 : Buffer full
At reset
RW ! ! ! ! ! ! ! 1!
0 0 0 0 0 0 0 1
0 : Transmit shift in progress 1 : Transmit shift completed 0 : No error 1 : Overrun error 0 : No error 1 : Parity error 0 : No error 1 : Framing error 0 : (OE) U (PE) U (FE) = 0 1 : (OE) U (PE) U (FE) = 1 Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "1."
Fig. 1.13B.14 Structure of Serial I/O status register
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Each bit of the Serial I/O status register is described below. 2 Transmit buffer empty flag (TBE, bit 0) This flag indicates the state of the Transmit buffer register. This bit is set to "1" after the data written in the Transmit buffer register is transferred to the Transmit shift register, and cleared to "0" after data is written into the Transmit buffer register. This flag is valid in both clock synchronous serial I/O and UART. 2 Receive buffer full flag (RBF, bit 1) This flag indicates the state of the Receive buffer register. When 1-byte data has been all input to the Receive shift register and then the receive data has been transferred from the Receive shift register to the Receive buffer register, this flag is automatically set to "1." When the transferred data has been read out from the Receive buffer register, the flag is automatically cleared to "0." If receive data is further input to the Receive shift register when the receive buffer full flag is "1" (without reading out the contents of the Receive buffer register), the overrun error flag is set to "1." The receive buffer full flag is valid in both clock synchronous serial I/O and UART. 2 Transmit shift completion flag (TSC, bit 2) This flag indicates the state of the transmit shift operation. When transmit data has been transferred to the Transmit shift register and then a shift operation has been started with the synchronous clock (transmission of the 1st bit of the transmit data), this flag is cleared to "0." When the shift operation has been completed (completion of transmission the last bit of the transmit data), the flag is set to "1." This flag is valid in both clock synchronous serial I/O and UART. 2 Overrun error flag (OE, bit 3) This flag indicates the receive data read state. If receive data is further input to the Receive shift register when the receive buffer full flag is "1" (without reading out the contents of the Receive buffer register), the overrun error flag is set to "1." This flag is cleared to "0" by any operation shown in Table 1.13B.8. This flag is valid in both clock synchronous Serial I/O and UART. 2 Parity error flag (PE, bit 4) This flag indicates a hardware check result on the even parity or odd parity in the UART. If there is a difference between the parity of received data and the set parity, the flag is set to "1." This flag is cleared to "0" by any operation shown in Table 1.13B.8. This flag is valid in the parity enable state in UART. 2 Framing error flag (FE, bit 5) This flag judges a frame synchronization error in UART. When the stop bit of receive data cannot be received at the set timing, the flag is set to "1." At stop bit detection, only the 1st stop bit is detected but the 2nd stop bit is not checked. This flag is cleared by any operation shown in Table 1.13B.8. This flag is valid in UART only.
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2 Summing error flag (SE, bit 6) This flag judges a serial I/O error. If one of an overrun error, a parity error and a framing error occurs, the flag is set to "1." This flag is cleared by any operation shown in Table 1.13B.8. This flag is valid in both clock synchronous serial I/O and UART. [Error flag clear method] The error flags (bit 3 to bit 6) in the Serial I/O status register can be cleared to "0" by the error flag clear methods shown in Table 1.13B.8. Table 1.13B.8 Error flag clear method Clear the serial I/O inter- Clear the receive enable bit Write dummy data into the Error flag rupt enable bit to "0." to "0." SIOSTS. Overrun error flag , , , Parity error flag x , , Framing error flag x , , Summing error flag x , ,
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(3) Serial I/O control register (SIOCON: Address 00E216) The Serial I/O control register exerts various types of control over the serial I/O, for example, transfer mode, clocks and pin function selection. All the bits of this register can be read and written by software. Figure 1.13B.15 shows a structure of the Serial I/O control register.
Serial I/O control register (7477/7478 group)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register (SIOCON) [Address 00E216] B 0 1 Name BRG count source selection bit (CSS) Serial I/O synchronous clock selection bit (SCS) Function 0 : f(XIN)/4 or f(XCIN)/4 1 : f(XIN)/16 or f(XCIN)/16 *In clock synchronous mode 0 : BRG output divided by 4 1 : External clock input *In UART mode 0 : BRG output divided by 16 1 : External clock input divided by 16 0 : P17/SRDY pin operates as ordinary I/O pin 1 : P17/SRDY pin operates as SRDY output pin 0 : When transmit buffer has emptied 1 : When transmit shift operation is completed
At reset
RW
0
0
2 SRDY output enable bit (SRDY)
VIn the UART mode, this bit is invalid.
0
3
Transmit interrupt source selection bit (TIC)
0
4 5 6
Transmit enable bit (TE) 0 : Transmit disabled 1 : Transmit enabled Receive enable bit (RE) 0 : Receive disabled 1 : Receive enabled Serial I/O mode 0 : Clock asynchronous selection bit (SIOM) serial I/O (UART) 1 : Clock synchronous 0 : Serial I/O disabled
(pins operates as ordinary I/O pins P14-P17)
0 0 0
7 Serial I/O enable bit (SIOE)
0
1 : Serial I/O enabled (pins operates as serial I/O pins RXD - SRDY) (Note) Note: Port P14-P17 are operates as the serial I/O pin only when the serial I/O enable bit is "1" (enable state). At this time, Port P1 7 is also used as an ordinary I/O port. In the UART mode, port P1 6 is used as an ordinary I/O port when the internal clock is selected.
Fig. 1.13B.15 Structure of Serial I/O control register
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Each bit of the Serial I/O control register is described below. 2 BRG count source selection bit (CSS, bit 0) This bit selects a count source to be input to the BRG. * "0": f(XIN)/4 * "1": f(XIN)/16 2 Serial I/O synchronous clock selection bit (SCS, bit 1) This bit selects a synchronous clock to be used for the serial I/O. q In the clock synchronous serial I/O * "0": The BRG output divided by 4 becomes a shift clock. * "1": The external clock (P16/SCLK pin input) becomes a synchronous clock. q In the UART * "0": The BRG output divided by 16 becomes a shift clock. * "1": The external clock (P16/SCLK pin input) divided by 16 becomes a synchronous clock. 2 SRDY output enable bit (SRDY, bit 2) This bit selects whether the P17/SRDY pin is used as P17 or as serial I/O pin SRDY or SRDY output disable. q In the clock synchronous serial I/O * "0": SRDY pin output disable (used as port P17) * "1": SRDY pin output enable (used as serial I/O pin SRDY) q In the UART The P17/SRDY pin is used as P17 regardless of the value of this bit. 2 Transmit interrupt request selection bit (TIC, bit 3) This bit determines a source for generating a transmit interrupt request. * "0": When the contents of the Transmit buffer register are transferred to the Transmit shift register, a transmit interrupt request is generated. * "1": When the shift operation of the Transmit shift register terminates, a transmit interrupt request is generated. 2 Transmit enable bit (TE, bit 4) This bit controls a transmit operation. q When the serial I/O enable bit (bit 7) is "0" (serial I/O disable) The transmit enable bit is invalid. q When the serial I/O enable bit (bit 7) is "1" (serial I/O disable) The control shown in Table 1.13B.9 is exerted. Table 1.13B.9 Transmit enable bit function Transmit enable bit P15/TXD pin function Transmit buffer empty flag 1 Cleared to "0" Flag function is valid. Transmit shift completion flag2 Cleared to "0" Flag function is valid.
0 Port P15 1 Serial I/O data transmit pin TXD 1: Bit 0 of Serial I/O status register 2: Bit 2 of Serial I/O status register
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2 Receive enable bit (bit 5) This bit controls the receive operation. q When the serial I/O enable bit (bit 7) is "1" (serial I/O enable), the control shown in Table 1.13B.10 is exerted. q When the serial I/O enable bit (bit 7) is "0" (serial I/O disable), this bit is invalid. Table 1.13B.10 Receive enable bit function Receive enable bit P14/RXD pin function Receive buffer full flag 1 Cleared to "0" Flag function is valid. Each error flag2 Cleared to "0" Flag function is valid.
0 Port P14 1 Serial I/O data transmit pin RXD 1: Bit 1 of Serial I/O status register 2: Bit 3,4,5 and 6 of Serial I/O status register
2 Serial I/O mode selection bit (bit 6) This bit selects the clock synchronous serial I/O or the UART. * "0": UART * "1": Clock synchronous serial I/O 2 Serial I/O enable bit (bit 7) This bit selects whether each of the P14/RxD, P15/TxD, P16/SCLK and P17/SRDY pins is used as a port or a serial I/O pin. When using the serial I/O, set this bit to "1." * "0": The respective pins become P14 to P17. * "1": The respective pins become serial I/O pins, RXD, TxD, SCLK, SRDY. Note: In the UART, when the internal clock is selected, the P16/SCLK pin can be used as port P16. However, for the P17/SRDY pin, take the following points into consideration. 2 In the clock asynchronous serial I/O When using the P17/SRDY pin as serial I/O pin SRDY, set the SRDY output enable bit (bit 2) to "1." 2 In the UART The P17/SRDY pin is used as P17 regardless of the value of the serial I/O enable bit.
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(4) UART control register (UARTCON: Address 00E316) The UART control register controls the UART transfer data format and the P15/TxD pin output type. Figure 1.13B.16 shows a structure of UART control register.
UART control register (7477/7478 group)
b7 b6 b5 b4 b3 b2 b1 b0
1111
UART control register (UARTCON) [Address 00E316] B Name Function 0: 8 bits 0 Character length selection bit (CHAS) 1: 7 bits 0: Parity checking disabled 1 Parity enable bit 1: Parity checking enabled (PARE) 0: Even parity 2 Parity selection bit (PARS) 1: Odd parity 3 Stop bit length 0: 1 stop bit selection bit (STPS) 1: 2 stop bits 4 Nothing is allocated for these bits. These are write to disabled bits. When these bits are read out, the 7 values are "1."
At reset
RW
0 0 0 0 1 1!
Fig. 1.13B.16 Structure of UART control register Each bit of the UART control register is described below. 2 Character length selection bit (CHAS, bit 0) This bit selects a data bit length of the UART transfer data format. * "0": 8-bit length * "1": 7-bit length 2 Parity enable bit (PARE, bit 1) This bit selects whether a parity check is made. * "0": No parity check (Parity error flag is invalid.) * "1": Parity check (Parity error flag is valid.) 2 Parity selection bit (PARS, bit 2) This bit selects a parity type of the UART transfer data format. * "0": Even * "1": Odd 2 Stop bit length selection bit (STPS, bit 3) This bit selects a stop bit length of the UART transfer data format. * "0": 1-stop bit * "1": 2-stop bit
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1.14 A-D converter
In the 7470/7471/7477/7478 group, the following A-D converter is incorporated. q Analog input pins...... 7470/7477 group: 4 channels (in common with Port P2) 7471/7478 group: 8 channels (in common with Port P2) q Conversion method ... Successive approximation comparison In the 7470/7471 group, when the A-D converter is not used, power dissipation can be suppressed by the VREF switch. (The 7477/7478 group is not provided with this function.) Figure 1.14.1 shows a block diagram of the A-D converter.
Data bus
b4
(Note 2)
b0
A-D control register
(Address 00D916)
P20/IN0 P21/IN1 P22/IN2 P23/IN3 P24/IN4 P25/IN5 P26/IN6 P27/IN7
A-D control circuit
A-D conversion interrupt request
Channel selector
Comparator
A-D conversion register
(Address 00DA16)
Switch tree
Resistor ladder
(Note 1) VREF switch (Note 2)
VSS
VREF
Notes 1. The 7470/7477 group is not provided with the P24 /IN4-P27/IN7 pins. 2. The 7477/7478 group is not provided with the VREF switch and the VREF connection selection bit (bit 4) of the A-D control register.
Fig. 1.14.1 A-D converter block diagram
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1.14 A-D converter
1.14.1 A-D conversion method The A-D conversion method is of successive approximation comparison. The reference voltage Vref generated internally is compared with the analog input voltage VIN which is input from the analog input pin (P20/IN0-P27/IN7), and its result is stored into each bit of the A-D conversion register (address 00DA16) successively to obtain a digital value. [Internal operation] After A-D conversion is started, the following operations are automatically performed. 1 The contents of the A-D conversion register is set to "0016." 2 The most significant bit (bit 7) of the A-D conversion register is set to "1." 3 The reference voltage Vref is input to the comparator. The reference voltage Vref is specified by the contents n of the A-D conversion register and the reference voltage VREF input from the VREF pin. An expression for the reference voltage Vref is shown below. Relational expression between Vref and VREF When n = 0 Vref = 0 When n = 1 to 255 Vref = VREF/256 x (n - 0.5) n: The values of A-D conversion register (decimal notation) 4 The reference voltage Vref and the analog input voltage VIN are compared with 8 times. Upon completion of each comparison, the comparison result is stored into the A-D conversion register. As the A-D conversion register changes, the reference voltage Vref changes. [1] Determination of the most significant bit (bit 7) of the A-D conversion register (in the 1st comparison) The reference voltage Vref and the analog input voltage VIN are compared. Bit 7 is determined according to its result as follows. If Vref < VIN , then bit 7 = "1." If Vref > VIN , then bit 7 = "0." [2] Determination of the bit 0 - 6 of the A-D conversion register (after the 2nd comparison). First, bit 6 of the A-D conversion register is set to "1." Next, the reference voltage Vref is compared with the analog input voltage VIN. Bit 6 is determined according to its result as follows. If Vref < VIN , then bit 6 = "1." If Vref > VIN , then bit 6 = "0."
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Likewise, bit 5 to bit 0 are determined according to comparison results of the 3rd to 8th comparisons. A digital value (contents of the A-D conversion register) corresponding to the analog input voltage VIN is determined bit by bit by these operations. Figure 1.14.2 shows the changes of the contents of the A-D conversion register and the reference voltage during A-D conversion. 5 After completion of A-D conversion, bit 3 of the A-D control register is set to "1" and an interrupt request is generated concurrently with the completion of A-D conversion. Notes 1: An A-D conversion result can be obtained by reading the A-D conversion register after bit 3 of the A-D control register is set to "1." 2: The A-D conversion result is held in the A-D conversion register until bit 3 of the A-D control register is set to "1" again after completion of the next A-D conversion.
Contents of A-D conversion register A-D conversion start
Reference voltage (V ref) [V]
00000000 10000000
VREF 2 VREF 2 VREF 2 VREF 2
0 - VREF
512 VREF 4 VREF 4
1st comparison start 2nd comparison start 3rd comparison start
1
1000000
- VREF
512 VREF 8
12100000 1234567
1
- VREF
512
8th comparison start
VREF VREF .....
4 .......
8 VREF 256
- VREF
512
A-D conversion completion (8th comparison completion)
12345678
Digital value corresponding to analog input voltage
m m : Value determined by m th (m=1 to 8) result
Fig 1.14.2 Contents of A-D conversion register and reference voltage during A-D conversion
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2 Conversion time q After a start of A-D conversion, this A-D conversion terminates after 50 cycles (12.5 s at f(XIN) = 8 MHz). q Main clock input oscillation frequency f(XIN)/2 is used as an operating clock for the A-D converter, so the A-D conversion time can be basically obtained by the following expression. A-D conversion time = 2 x conversion cycle (50: cycles) f(XIN)
Note: Because the comparator is configurated by capacity coupling, use the A-D converter in the following condition. f(XIN) > 1 MHz Accordingly, use the A-D converter in the condition that bit 7 of the CPU mode register (address 00FB16) is "0" (ordinary mode).
[Setting method] In the 7470/7471 group 1 Clear the bit of the Port P2 direction register corresponding to the used analog input pin to "0" (input mode). 2 Clear the port pull-up control bit corresponding to the used analog input pin to "0" (no pull-up). 3 Clear the A-D conversion interrupt request bit of the Interrupt request register 1 to "0." Note: After A-D conversion is started, the A-D conversion interrupt request bit is not cleared to "0" automatically. 4 When using an A-D conversion interrupt, set the A-D conversion interrupt enable bit to "1" to provide an interrupt enable state. 5 Set the A-D control register as follows. q Select an analog input pin by the analog input pin selection bit. q Set the VREF connection selection bit to "1" and connect VREF to a ladder resistor. 6 Wait for 1.0 s or more as VREF stabilizing time. 7 Clear the A-D conversion end bit of the A-D control register to "0." (With this setting, A-D conversion is started.) In the 7477/7478 group 1 Clear the A-D conversion interrupt request bit of the Interrupt request register 1 to "0." Note: After A-D conversion is started, the A-D conversion interrupt request bit is not cleared to "0" automatically. 2 When using an A-D conversion interrupt, set the A-D conversion interrupt enable bit to "1" to provide an interrupt enable state. 3 Set the A-D control register as follows. q Select an analog input pin by the analog input pin selection bit. q Clear the A-D conversion end bit to "0." (With this setting, A-D conversion is started.) Don't read the contents of the A-D conversion register during A-D conversion. For register setting, refer to "Table 1.14.1 Setting at A-D Conversion."
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Processing after conversion 1 A termination of conversion can be verified by any of the following operations. q State of A-D conversion end bit. q State of A-D conversion interrupt request bit. q Branch to A-D conversion interrupt routine. 2 Read the A-D conversion register to obtain a conversion result. Notes 1: Be sure to connect VREF to a ladder resistor during A-D conversion (7470/7471 group). 2: A-D conversion is restarted at the time when the A-D conversion end bit (bit 3) of the A-D control register is cleared to "0" during A-D conversion. Table 1.14.1 Setting at A-D conversion Register 1 Port P2 direction register(P2D: Address 00C516) (7470/7471 group)
2 Port P1-P4 pull-up control register (7470 group) Port P1-P5 pull-up control register (7471 group) (Address 00D116)
3 Interrupt request register 1 (IR1: Address 00FC16) 4 Interrupt control register 1 (IE1: Address 00FE16) 5 A-D conversion control register (ADCON: Address 00D916)
Value Clear the bit corresponding to the used analog input pin (one of pins P20/IN0 to P27/ b7 IN7) to "0" (input mode). Note: In the 7470 group, only pins P20/IN0 to P23/IN3 are available. b2 0: P20 to P23 are not pulled up. Note: When one of pins P20/IN0 to P23/IN3 is used as an analog input pin b3 0: P24 to P27 are not pulled up. Note: When one of pins P24/IN4 to P27/IN7 is used as an analog input pin (7471 group) b7 0: A-D conversion interrupt disabled b7 1: A-D conversion interrupt enabled b2, b1, b0 * 000: P20/IN0 * 001: P21/IN1 * 010: P22/IN2 * 011: P23/IN3 * 100: P24/IN4 * 101: P25/IN5 * 110: P26/IN6 * 111: P27/IN7 Set the value corresponding to the used analog input pin. Note: In the 7470/7477 group, only pins P20/ IN0 to P23/IN3 are available. b3 0: During conversion (A-D conversion is started.) b4 1: VREF connection (7470/7471 group) b7 Fix this bit to "0." Bit b0
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1.14.2 Pins The pins used in the A-D converter are described below. (1) Analog input pin (P20/IN0 to P27/IN7) (P20/IN0 to P23/IN3 in the 7470/7477 group) q The analog input pin is an input pin for analog voltage. q Apply a voltage of VSS (AVSS) - VREF to this pin. q This pin is used in common with P20 to P27 (P20 to P23 in the 7470/7477 group). When using the A-D converter, select a pin to be used as an analog input pin by bit 2 to bit 0 of the A-D control register (ADCON: address 00D916). Use the A-D converter in the following condition in the 7470/7471 group. * When the bit of the Port P2 direction register, which corresponds to the used analog input pin, is "0" (input mode) * When the bit of the Pull-up control register, which corresponds to the used analog input pin, is "0" (no pull-up) (2) Reference voltage input pin (VREF) q The reference voltage input pin is an input pin for reference voltage. q In the 7470/7471 group: Input a voltage of VCC/2 (>2) - VCC [V]. In the 7477/7478 group: Input a voltage of 2 - VCC [V]. (3) Analog power source input pin (AVSS) q Analog power source input pin is an input pin for GND. q Apply the same potential as the VSS pin to this pin. q This pin is dedicated to the 56P6N-A package product of the 7471/7478 group. 1.14.3 Notes on use When using the A-D converter, take the following points into consideration. 2 The comparator is configured by capacity coupling, so the charge is lost if the clock input oscillation frequency is low. q Set f(XIN) at 1 MHz or more during A-D conversion. q Don't execute the STP instruction during A-D conversion. 2 Apply a voltage of VCC/2 (>2) - VCC [V] to the reference voltage input pin VREF. Note that if the reference voltage is lowered below the above valve, the A-D conversion precision will be degraded. 2 Apply the same potential as that of the VSS pin to the analog power supply voltage input pin AVSS. The AVSS pin is dedicated to the 56P6N-A package product of the 7471/7478 group. 2 In the 7470/7471 group, clear the bit of the Port P2 direction register which corresponds to the used analog input pin to "0" (input mode). 2 In the 7470/7471 group, clear the bit of the Pull-up control register which corresponds to the used analog input pin to "0" (no pull-up).
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1.14.4 References 2 Definition of A-D conversion precision The definition of A-D conversion precision is described. Refer to the definition of A-D conversion precision shown in Figure 1.14.3. (1) Relative precision q Zero transition error (VOT) Deviation of the input voltage, at which A-D conversion output data changes from "0" to "1," from the ideal A-D conversion characteristics between 0 and VREF VOT = (VO - 1 VREF x 256 )/1LSB [LSB] 2
q Full-scale transition error (VFST) Deviation of the ideal A-D conversion characteristics between 0 and VREF of the input voltage when the A-D conversion output data changes from "255" to "254". VFST = {(VREF - 3 VREF x ) - V254}/1LSB [LSB] 2 256
q Non-linearity error Deviation of the real A-D conversion characteristics from the ideal characteristics between V0 and V254 Non-linearity error = {Vn - (1LSB x n + VO)}/1LSB [LSB] q Differential non-linearity error Deviation of the input voltage required to change output data by "1" from the ideal characteristics between V0 and V254 Differential non-linearity error = {(Vn+1 - Vn) - 1LSB}/1LSB [LSB]
(2) Absolute precision q Absolute precision Deviation of the real A-D conversion characteristic from the ideal characteristics between 0 and VREF. Absolute precision = {Vn - 1LSB x (n + 1 )}/1LSB [LSB] 2
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Output data
255 254
Full-scale transition error (VFST)
3 2 LSB
Differential non-linearity error
1LSB at relative accuracy n+1 n Actual A-D conversion characteristics
Ideal A-D conversion characteristics between 0 and VREF
Non-linearity error Absolute accuracy
1LSB at absolute accuracy 1 2 LSB 1
Ideal A-D conversion characteristics between V0 and V254
Zero transition error (VOT)
0
V0
V1
Vn
Vn+1
V254
VREF
Analog voltage
Fig. 1.14.3 Definition of A-D conversion precision Vn: Analog input voltage when output data changes from "n" to "n + 1" (n = 0 - 254). V254 - VO (V) 1LSB at relative precision 254 VREF (V) 1LSB at absolute precision * 1LSB = 256 * 1LSB =
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1.14.5 Related registers (1) A-D conversion register (AD: Address 00DA16) The A-D conversion register stores A-D conversion results. This register is a read-only type. Figure 1.14.4 shows a structure of the A-D conversion register.
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (AD) [Address 00DA16] B Function
At reset
RW !
0 This is a read-only register to store A-D to conversion results. 7
?
Fig. 1.14.4 Structure of A-D conversion register (2) A-D control register (ADCON: Address 00D916) The A-D control register consists of bits that exerts various types of control over the A-D converter. Figure 1.14.5 shows a structure of the A-D control register.
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A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
0
A-D control register (ADCON) [Address 00D916] B 0 1 2 3 4
A-D conversion end bit (Note 2) VREF connection selection bit
Name A-D input selection bits
0 0 0 0 1 1 1 1
b2 b1 b0
Function
0 0 1 1 0 0 1 1 0 : P20/IN0 1 : P21/IN1 0 : P22/IN2 1 : P23/IN3 0 : P24/IN4 1 : P25/IN5 0 : P26/IN6 1 : P27/IN7
At reset
RW
0 0
(Note 1)
0 1
0 : Under conversion 1 : End conversion 0 : The VREF pin is
separated from the comparison voltage VThe 7477/7478 group is not generator. provided with this bit. 1 : The VREF pin is This bit is undefined at connected to reset. comparison voltage generator.
0
Nothing is allocated for these bits. 5, 6 These are write disabled bits and are undefined at reading. 7 Fix this bit to "0."
? 0
?! 00
Notes 1: Since the 7470/7477 group is not provided with pins P24-P27, do not set. 2: *A-D conversion is started by setting bit 3 to "0." *Writing "0" into bit 3 is valid. Even if "1" is written into bit 3, this bit is not set to "1." Accordingly, when writing a value into the A-D control register without affecting bit 3, set bit 3 to "1."
Fig. 1.14.5 Structure of A-D control register Each bit of the A-D control register is described below. 2 Analog input pin selection bit (Bit 2 to 0) These bits select an analog input pin. Pins that are not used as analog input pins of P2 function as programmable I/O ports (input ports in the 7477/7478 group). 2 A-D conversion end bit (Bit 3) This bit indicates the operation state of the A-D converter. This bit is cleared to "0" during A-D conversion and set to "1" upon termination of A-D conversion. A-D conversion is started by clearing this bit to "0." (At the time when the bit is cleared to "0" during A-D conversion, A-D conversion is restarted.) 2 VREF connect selection bit (Bit 4) (The 7477/7478 group is not provided with this bit.) This bit connects the VREF pin to a ladder resistor. When using the A-D converter, be sure to set this bit to "1." When the A-D converter is not used, power consumption can be reduced by clearing this bit to "0."
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1.15 Reset
1.15 Reset
The microcomputer is reset by applying the "L" level to the RESET pin for 2 s or more when the power source voltage is within the standard value range. After that, when the "H" level is applied to the RESET pin, the reset state of the microcomputer is released, so that the program is run starting with the reset vector address. 1.15.1 Operation description Figure 1.15.1 shows an internal processing sequence after reset release.
VCC
XIN Internal clock 2 s or more
RESET
32768 counts of X IN pin input signal Internal reset Address bus Data bus
FFFE16 FFFF16 AL,AH
AL
AH
SYNC Internal clock : CPU reference clock frequency after reset release) AH, AL : Content of reset vector address SYNC : CPU operation code fetch cycle (This is a internal signal, so that it cannot be observed from the external unit.) : Undefined
= f(XIN)/2 (ordinary mode immediately
Fig. 1.15.1 Internal processing sequence after reset release
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When the "H" level is applied to the RESET pin at the reset state, the contents of timer 3 and timer 4 and the count source are automatically set as shown in Table 1.15.1, so that the internal reset state is released by an overflow of timer 4. Table 1.15.1 Timer 3 and 4 at reset Item Timer 3 Setting value FF16 count source f(XIN)/16
Timer 4 0716 overflow of timer 3
After the "H" level is applied to the RESET pin, only the main clock oscillates regardless of the oscillation state precedent to the reset state, so that the microcomputer starts to operate in the ordinary mode. The XCIN pin and the XCOUT pin become P50 and P51, respectively. After the reset state is released, the microcomputer runs the program starting with the high-order address corresponding to the contents of address FFFF16 and the low-order address corresponding to the contents of address FFFE16. Note: The 7470/7477 group is not provided with the XCIN and XCOUT pins.
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1.15.2 Internal status immediately after reset release Figure 1.15.2 shows an internal register status immediately after reset release.
Address (1) (2) (3) (4) (5) (6) (7) (8) (9) Port P0 direction register (P0D) Port P1 direction register (P1D) Port P2 direction register (P2D)
(The 7477/7478 group is not provided.)
(C116)*** (C316)*** (C516)*** (C916)*** (D016)*** (D116)*** (D416)*** (D916)*** (DC16)*** (E116)*** (E216)*** (E316)*** (F216)*** (F316)*** (F716)*** (F816)*** (F916)*** (FA16)*** (FB16)*** (FC16)*** (FD16)*** (FE16)*** (FF16)***
0016 0016 0016 0000 0016 0 00000 000000 0 01000 0016 10000000 0016 11110000 FF16 0716 00 0016 0016 00 0000 000 00 000 0000 000 000 0000 000
Contents of address FFFF 16 Contents of address FFFE 16
Port P4 direction register (P4D) Port P0 pull-up control register Port P1-P5 pull-up control register
(In the 7470/7477 group, port P1-P4 pull-up control register)
Edge polarity selection register (EG) A-D control register (ADCON) Serial I/O mode register (SM)
(The 7477/7478 group is not provided.)
(10) Serial I/O status register (SIOSTS)
(The 7470/7471 group is not provided.)
(11) Serial I/O control register (SIOCON)
(The 7470/7471 group is not provided.)
(12) UART control register (UARTCON)
(The 7470/7471 group is not provided.)
(13) Timer 3 (T3) (14) Timer 4 (T4) (13) Timer FF register (TF) (14) Timer 12 mode register (T12M) (15) Timer 34 mode register (T34M) (16) Timer mode register 2 (TM2) (17) CPU mode register (CPUM) (18) Interrupt request register 1 (IR1) (19) Interrupt request register 2 (IR2) (20) Interrupt control register 1 (IE1) (21) Interrupt control register 2 (IE2) (22) Program counter (PC H) (PCL) (23) Processor status register (PS) : The contents are undefined at reset release.
1
Note : The contents of all other registers and RAM are undefined at reset, so set their initial valves. The bits are different depending on the product. Refer to the structure of each register.
Fig. 1.15.2 Internal status immediately after reset release
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1.15.3 Notes on use 1. The timer continues to perform a count operation after reset release. 2. After the reset state is released, the microcomputer runs the program starting with the high-order address corresponding to the contents of address FFFF16 and the low-order address corresponding to the contents of address FFFE16. 3. After the "H" level is applied to the RESET pin, only the main clock oscillates regardless of the oscillation state precedent to the reset state, so that the microcomputer starts to operate in the ordinary mode. The XCIN pin and the XCOUT pin become P50 and P51, respectively. (The 7470/7477 group is not provided with the XCIN and XCOUT pins.) 4. When the STP instruction is executed in the ordinary mode, I/O ports are held in the state just precedent to a stop of system clock oscillation. After that, the I/O ports are put into the input mode after a reset operation of the microcomputer is performed, so that they go to the high-impedance state.
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1.16 Oscillation circuit
The 7470/7471/7477/7478 group has the following circuits to obtain clocks required for operations. * 7470/7477 group: Main clock oscillation circuit * 7471/7478 group: Main clock oscillation circuit and sub-clock oscillation circuit 1.16.1 Oscillation circuit (1) Clock generating circuit The clock generating circuit controls the oscillation of the oscillation circuit and a generated clock (internal clock ) is supplied to the CPU and peripheral units. Figure 1.16.1 shows a clock generating circuit block diagram.
Interrupt disable flag I Interrupt request
Reset Internal system clock selection bit (CM 7) Main clock (XIN-XOUT) stop bit (CM6)
Q
S
STP instruction
R
XIN
XCIN XOUT
S
Q
1/2 XCOUT
Internal system clock selection bit (CM7) Internal clock
WIT instruction Reset
R
1/2
Timer 3 count source selection bits 1/8 T34M1 T34M2
S
Q
STP instruction
R
CNTR1
Timer 1 or timer 2 overflow signal Timer 3 count stop bit (T34M0)
Timer 3
Timer 4 count stop bit (T34M3) .
Timer 4 count source selection bits T34M4 T34M5 Timer 4
Note : The 7470/7477 group is not provided with pins XCIN and XCOUT.
Fig. 1.16.1 Clock generating circuit block diagram
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This oscillation circuit can stop and start oscillation. * XIN-XOUT oscillation circuit ......................... Main clock f(XIN) * XCIN-XCOUT oscillation circuit .................... Sub-clock f(XCIN) There are two oscillation circuits (the main clock only in the 7470/7477 group) as shown above. The clock obtained by dividing a signal input to the clock input pin XIN or XCIN becomes an internal clock + which is used as a reference for operations. +: The internal clock varies with the operation modes of the microcomputer. * Ordinary mode ................ Signal input to the XIN pin divided by 2 * Low-speed mode ............ Signal input to the XCIN pin divided by 2 (2) Oscillation circuit using a ceramic resonator or a crystal oscillator An oscillation circuit can be formed by connecting a ceramic resonator or a crystal oscillator between the XIN pin and the XOUT pin and between the XCIN pin and the XCOUT pin. For a circuit example, refer to "Chapter 2 Application, 2.7 Oscillation Circuit." Please ask the oscillator maker for information on circuit constants and then set the value recommended by the maker. (3) External clock input circuit It is also possible to supply a clock to the oscillation circuit from the outside. As an external clock to be input to the XIN and XCIN pins, use a pulse signal with a duty ratio of 50 %. At this time, make the XOUT and XCOUT pins open. For a circuit example, refer to "Chapter 2 Application, 2.7 Oscillation Circuit." Note: Because the 7470/7477 group is not provided with the XCIN and XCOUT pins, the sub-clock f(XCIN) is not available.
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1.16.2 Sub-clock oscillation circuit In the 7471/7478 group, the sub-clock f(XCIN) is available when the P50/XCIN pin and the P51/XCOUT pin are used as the XCIN pin and the XCOUT pin. The power supplied to the sub-clock oscillation circuit is given through a voltage reduction regulator to reduce power dissipation in the sub-clock mode. That is, power is reduced by reducing the voltage applied to the VCC pin by the voltage reduction regulator. The supply voltage to this oscillation circuit can be set to one of the 2 stages of high power mode and low power mode in bit 5 of the CPU mode register. Notes 1: When using the sub-clock, set f(XCIN) < 50 kHz < f(XIN)/3. 2: When using the sub-clock f(XCIN) in the 7471/7478 group, set the P50-P53 pull-up control bit (bit 6) of the P1-P5 pull-up control register to "0" and disconnect the pull-up transistor of the P50/XCIN pin and P51/XCOUT pin. 3: When using the sub-clock as the internal clock , use it in one of the following states. q Fix the XCOUT drive capacity to the high power mode (set the XCOUT drive capacity selection bit of the CPU mode register to "1"). q When fixing the XCOUT drive capacity to the Low power mode (set the XCOUT drive capacity selection bit of the CPU mode register to "0"), lower the value of the resistor Rd+ in the subclock oscillation circuit to a level at which the oscillation of f(XCIN) does not stop. + "Resistor Rd": Refer to the circuit example in "Chapter 2 Application, 2.7 Oscillation circuit."
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1.16.3 Oscillation operation (1) Oscillation operation The microcomputer is put into the ordinary mode at reset release. At this time, only the main clock oscillates and the P50/XCIN pin and the P51/XCOUT pin function as input ports P50 and P51. Notes 1: The 7470/7477 group is not provided with XCIN and XCOUT pins. 2: When using the sub-clock f(XCIN) in the 7471/7478 group, set the P50-P53 pull-up control bit (bit 6) of the P1-P5 pull-up control register to "0" and disconnect the pull-up transistor of the P50/XCIN pin and P51/XCOUT pin. 2 Ordinary mode The clock resulting from dividing a signal input to the XIN pin by 2 becomes internal clock . Changing the mode to the low-speed mode (7471/7478 group) Execute the following procedure. 1 Set the P50, P51/XCIN, XCOUT selection bit (bit 4) of the CPU mode register to "1" (XCIN, XCOUT). 2 Set the XCOUT drive capacity selection bit (bit 5) of the CPU mode register to "1" (High power). 3 Generate oscillation stabilizing wait time of f(XCIN) by software. 4 Set the system clock selection bit (bit 7) of the CPU mode register to "1" f(XCIN). At that time, set the XCOUT drive capacity selection bit to "0" (low power) as required. 2 Low-speed mode (7471/7478 group) The clock resulting from dividing a signal input to the XCIN pin by 2 becomes internal clock . In the low-speed mode, a low power dissipation operation can be attained by setting the main clock (XIN-XOUT) stop bit (bit 6) of the CPU mode register to "1." Changing the mode to the ordinary mode Execute the following procedure. 1 Clear the main clock (XIN-XOUT) stop bit (bit 6) of the CPU mode register to "0" (oscillate). 2 Generate oscillation stabilizing wait time of f(XIN) by software. 3 Clear the system clock selection bit (bit 7) of the CPU mode register to "0" f(XIN). Notes 1: Switch between the ordinary mode and the low-speed mode after the oscillation of the main clock and the sub-clock becomes stable. For the oscillation stablizing time, ask the oscillator maker for information. 2: Use the low-speed mode in one of the following states. q Fix the XCOUT drive capacity to the high power mode (set the XCOUT drive capacity selection bit of the CPU mode register to "1"). q When fixing the XCOUT drive capacity to the Low power mode (clear the XCOUT drive capacity selection bit of the CPU mode register to "0"), lower the value of the resistor Rd+ in the subclock oscillation circuit to a level at which the oscillation of f(XCIN) does not stop. + Resister Rd: Refer to a example of circuit in "chapter 2 application, 2.7 Oscillation circuit." 3: When using the sub-clock especially, it takes a long time until the oscillation becomes stable. When the ordinary mode is changed to the stop mode while the sub-clock is in the oscillation state and then the ordinary mode is restored from the stop mode, the oscillation of the sub-clock is not stabilized even if the main clock becomes stable and the CPU is restored.
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(2) Oscillation operation in the stop mode After the stop mode is provided by execution the STP instruction, all oscillation stops. After that, when the previous mode is restored from the stop mode by inputting the reset signal or generating a restoration interrupt request, the oscillation starts. For the details of the stop mode, refer to "1.17.1 Stop mode." (3) Oscillation operation in the wait mode When the wait mode is provided by execution the WIT instruction, the internal clock supplied to the CPU stops. When the previous mode is restored from the wait mode by inputting the reset signal or generating an interrupt request, the supply of internal clock to the CPU starts. For the details of the wait mode, refer to "1.17.2 Wait mode." (4) State transitions of internal clock Refer to "1.18 State transitions."
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1.16.4 Oscillation stabilizing time In the oscillation circuit using a ceramic resonator or a crystal oscillator, the oscillation becomes unstable for a certain period at a start of oscillation of the oscillator. The time required for stabilization of oscillation is called oscillation stabilizing time. A proper oscillation stabilizing wait time fit for the used oscillation circuit is required. For the oscillation stabilizing time, ask the oscillator maker for information. (1) Oscillation stabilizing wait time at power on In the 7470/7471/7477/7478 group, the oscillation stabilizing wait time for 32768 counts of the XIN pin input signal is automatically generated in the period from power on to reset release. Figure 1.16.2 shows a oscillation stabilizing wait time after power on.
2.7V VCC
V
2 s or more RESET
XIN Oscillation stabilizing wait time 32768 counts of X IN pin input signal Internal reset
Release internal reset state V : At f(XIN) = (2.2 VCC - 2) MHz
Fig. 1.16.2 Oscillation stabilizing wait time after power on (2) Oscillation stabilizing wait time at recovery from stop mode In the stop mode, oscillation stops. When the previous mode is restored from the stop mode by inputting a reset signal or generating an interrupt, the oscillation stabilizing wait time for 32768 counts of the XIN pin input signal or the XCIN pin input signal is automatically generated in the same way as the power on time. q At recovery by reset, f(XIN) becomes a count source that generates oscillation stabilizing wait time. q At recovery by interrupt, the count source of timer 3 set immediately before execution of the STP instruction becomes a count source that generates oscillation stabilizing wait time. Note that when f(XIN) is the system clock, the oscillation of the f(XCIN) side may not be stabilized after the lapse of this oscillation stabilizing wait time. For the details of the stop mode, refer to "1.17.1 Stop mode." Note: In the 7470/7477 group, f(XCIN) is not available.
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1.16.5 Notes on use 1. When inputting the external clock to the XIN pin or the XCIN pin, use a pulse signal with a duty ratio of 50 % as an input signal. At this time, make the XOUT pin and the XCOUT pin open. Refer to a example of circuit in "Chapter 2 application, 2.7 Oscillation circuit." 2. When using the sub-clock f(XCIN) in the 7471/7478 group, set f(XCIN) < 50 kHz < f(XIN)/3. 3. In the 7471/7478 group, switch between the ordinary mode and the low-speed mode after the oscillation of the main clock and the sub-clock becomes stable. For the oscillation stabilizing time, ask the oscillator maker for information. 4. Use the low-speed mode in one of the following states. * Fix the XCOUT drive capacity to the high power mode (Set the XCOUT drive capacity selection bit of the CPU mode register to "1"). * When fixing the XCOUT drive capacity to the Low-power mode (clear the XCOUT drive capacity selection bit of the CPU mode register to "0"), lower the value of the resistor Rd+ in the sub-clock oscillation circuit to a level at which the oscillation of f(XCIN) does not stop. + Resister Rd: Refer to a example of circuit in "Chapter 2 application, 2.7 Oscillation circuit." 5. When using the sub-clock f(XCIN) in the 7471/7478 group, it takes a long time until the oscillation becomes stable. When the ordinary mode is changed to the stop mode while the sub-clock is in the oscillation state and then the ordinary mode is recovered from the stop mode, the oscillation of the sub-clock is not stabilized even if the main clock becomes stable and the CPU is restored. Note: In the 7470/7477 group, the sub-clock f(XCIN) is not available because neither XCIN pin nor XCOUT pin is provided.
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1.17 Low-power dissipation function
The 7470/7471/7477/7478 group is provided with a function to put the CPU into a wait state with low-power dissipation by stopping the CPU operation by softoware. The low-power dissipation function has the following 2 modes. q Stop mode by a STP instruction q Wait mode by a WIT instruction Figure 1.17.1 shows the operation states of the microcomputer at low-power dissipation and Figure 1.17.2 shows a state transition.
STP mode
WIT mode
Oscillation stops Oscillation is operating CPU
Peripheral device Timer A-D converter Serial I/O
Stop
Stop
Stop
Note : When using an external clock, timer and serial I/O are operating.
Operating
External interrupt
Operating
Operating
Fig. 1.17.1 Operation states of the microcomputer at low-power dissipation
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STP mode
Reset Interrupt Reset
WIT mode
Interrupt
Only RAM is held and the other registers are reset.
Registers except timers 3, 4 and RAM are held.
Registers and RAM are held.
Oscillation stabilizing wait time : f(XIN)/16 is counted Reset release (Program execution from reset vector)
Oscillation stabilizing wait time: 32768 counts of the specified count source are counted No oscillation stabilizing wait time
Interrupt processing
Proceed to the next address of the STP or WIT instruction (Program is continued)
Fig. 1.17.2 State transition at low-power dissipation
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1.17.1 Stop mode To switch to the stop mode, execute the STP instruction. In the stop mode, the oscillation of both f(XIN) and f(XCIN) stops and the internal clock stops. Accordingly, the CPU stops and the peripheral units also stop. This leads to a reduction of power dissipation. Note: In the 7470/7477 group, the f(XCIN) is not available. (1) State of stop mode Table 1.17.1 shows a state of stop mode. Note: When the STP instruction is executed, "FF16" and "0716" are automatically set in timer 3 and timer 4, respectively.
Table 1.17.1 State of stop mode Item State of stop mode Oscillation Stop CPU Stop State at execution STP I/O port P0 to P5 instruction is held. When internal count source selected : Stop Timer When external count source selected : Operate Internal clock mode: Stop Serial I/O External clock mode: Operate Held RAM Held (except timer3, timer4) SFR Held CPU register + + CPU register : The following 6 registers are incorporated in the CPU. * Accumulator * Index register X * Index register Y * Stack pointer * Program counter * Processor status register
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(2) Releasion of stop mode The stop mode is released by inputting a reset signal or generating an interrupt request. There is a difference in restore processing from the stop mode between the use of reset input and the use of interrupt. 2 Recovery by reset input The microcomputer is reset by applying the "L" level to the RESET pin for 2 m s or more in the stop mode, thereby releasing the stop mode. After the stop mode is released, oscillator starts. (At this time, the inside is in the reset state.) The reset state is released after 32768 counts of the XIN pin input after the "H" level is applied to the RESET pin. At a start of oscillation of the oscillator, the oscillation is unstable. It takes time before stabilization of oscillation (oscillation stabilizing time). The oscillation stabilizing wait time is secured by the time for holding this internal reset state. For the details of the reset, Refer to "1.15 Reset." Note: When the stop mode is released, the contents of the RAM before reset are held. However, the contents of the CPU register and the SFR cannot be held but are reset. Figure 1.17.3 shows the oscillation stabilizing wait time at recovery from stop mode by reset input.
Stop mode VCC 2 s or more Oscillation stabilizing wait time : 32768 counts of X IN pin input signal RESET XIN (Note)
Undefined XIN: in high-impedance state XOUT: "H"
Execute STP instruction
Recovered by reset input
Note: No waveform may be input to XIN (in low-speed mode).
Fig. 1.17.3 oscillation stabilizing wait time at recovery from stop mode by reset input
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2 Recovery by interrupt When an interrupt request is generated in the stop mode, this stop mode is released and oscillation is started. The interrupt sources that are available for recovery are shown below. q q q q q INT0, INT1 CNTR0, CNTR1 Serial I/O at using external clock Timer (timer 1, timer 2) at using external clock Key input (key on wake up)
However, when the above interrupt sources are used for recovery from the stop mode, perform the following setting and then execute the STP instruction to permit an interrupt to be used. [Register setting] 1 Clear the interrupt enable bit of timer 3 and timer 4 to "0." (Disabled) 2 Set the count stop bit of timer 3 and timer 4 to "1." (Stop) 3 Select a count source of timer 3 in consideration of the oscillation stabilizing time of the oscillator. Note: Re-set the previous count source at recovery. 4 Clear the interrupt request bit of the interrupt source to be used for recovery to "0." 5 Set the interrupt enable bit of the interrupt source to be used for recovery to "1."(Enabled) 6 Clear the count stop bit of timer 3 and timer 4 to "0." (Count starts) 7 When using the sub-clock, set the XCOUT drive capacity to high power. (Refer to "1.16.2 Subclock oscillation circuit.") 8 Clear the interrupt disable flag I to "0." (Enabled) Note: In the stop mode, A-D conversion operation stops. Accordingly, execute the STP instruction after termination of the A-D conversion. For the details of the Interrupt, refer to "1.11 Interrupts." At a start of oscillation of the oscillator, the oscillation is unstable. It takes time before stabilization of oscillation (oscillation stabilizing time). At recovery by interrupt, the waiting time for the supply of internal clock to the CPU by timer 3 and timer 4 +1 is automatically generated +2. The oscillation stabilizing time of the system clock side is secured by this waiting time. Figure 1.17.4 shows an example of restoration sequence from the stop mode by the INT0 interrupt. +1: When the STP instruction is executed, "FF16" and "0716" are automatically set in the counter and latch of timer 3 and the counter and latch of timer 4, respectively. +2: The count source is supplied to timer 3 immediately after a start of oscillation, thereby starting a count operation. The supply of internal clock to the CPU is started when timer 4 overflows.
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qWhen recovering from stop mode by using INT 0 interrupt (rising edge selected)
Stop mode Oscillation stabilizing wait time 2048 counts of timer 3 count source (Note)
XIN or XCIN
INT0 pin
Undefined XIN, XCIN ; in high-impedance stat XOUT ; "H"
"FF16"
Count down
Timer 3
"0716"
Timer 4 INT0 interrupt request bit
Operating
Peripheral device CPU
Stop Stop
Operating Operating
Operating
*STP instruction *INT0 interrupt signal input execution (INT0 interrupt request occurs) *Oscillation start *Timer 3 count start
*Timer 4 overflow *Start supplying internal clock to CPU *Accept INT0 interrupt request
Note: The count source is a count source of timer 3 before execution of the STP instruction.
Fig. 1.17.4 Example of recovery sequence from stop mode by INT0 interrupt
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1.17.2 Wait mode To switch to the wait mode, execute the WIT instruction. In the wait mode, oscillation is continued but the internal clock stops. Accordingly, the CPU stops but the peripheral units operate since oscillation is continued. (1) State of wait mode Table 1.17.2 shows a state of wait mode. Table 1.17.2 State of wait mode Item State of wait mode Oscillation Operate CPU Stop State at execution WIT instrucI/O port P0 to P5 tion is held. Timer Operate Serial I/O Operate RAM Held SFR Held CPU register+ Held + CPU register : The following 6 registers are incorporated in the CPU. * Accumulator * Index register X * Index register Y * Stack pointer * Program counter * Processor status register
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(2) Releasion of wait mode The wait mode is released by inputting a reset signal or generating an interrupt request. There is a difference in restore processing from the wait mode between the use of reset input and the use of interrupt. 2 Recovery by reset input The microcomputer is reset by applying the "L" level to the RESET pin for 2 ms or more in the wait mode, thereby releasing the wait mode. After the wait mode is released by inputting the reset signal, the supply of internal clock to the CPU is started. The reset state is released after 32768 counts of the XIN pin input signal after the "H" level is applied to the RESET pin. For the details of the reset, refer to "1.15 Reset." Note: When the wait mode is released, the contents of the RAM before reset are held. However, the contents of the CPU register and the SFR cannot be held but are reset. Figure 1.17.5 shows the reset input time.
Wait mode VCC 2 s or more Oscillation stabilizing wait time : 32768 counts of XIN pin input signal RESET
XIN (Note) Execute WIT instruction Recovered by reset input
Note: No waveform may be input to XIN (in low-speed mode).
Fig. 1.17.5 Reset input time
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2 Recovery by interrupt In the wait mode, oscillation is continued. Accordingly, as soon as the wait mode is released, an instruction is executed. When an interrupt request is generated in the wait mode, this wait mode is released and the supply of internal clock to the CPU is started. At the same time, the interrupt request used for recovery is accepted, so that the interrupt processing routine is executed. The interrupt sources that are available for recovery are shown below. q q q q q q INT0, INT1 CNTR0, CNTR1 Serial I/O A-D conversion Timer 1 to timer 4 Key input (key on wake up)
However, when the above interrupt sources are used for recovery from the wait mode, perform the following setting and then execute the WIT instruction to permit an interrupt to be used. [Register setting] 1 Clear the interrupt request bit of the interrupt source to be used for recovery to "0."(No request) 2 Set the interrupt enable bit of the interrupt source to be used for recovery to "1."(Enabled) 3 Clear the interrupt disable flag I to "0." (Enabled) For the details of the Interrupt, refer to "1.11 Interrupts."
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1.17.3 Notes on use [Notes on use of the stop mode] 2 Clock after recovery After recovery from the stop mode by interrupt, the contents of the CPU mode register before execution of the STP instruction are held. Accordingly, if both f(XIN) and f(XCIN) were oscillating before execution of the STP instruction, the oscillation of both f(XIN) and f(XCIN) is restarted after recovery by interrupt. In the above case, if f(XIN) is set as the system clock, the oscillation stabilizing wait time for 32768 counts of the XIN pin input signal is secured at recovery from the stop mode. Note that the f(XCIN) clock may not be stabilized even after the lapse of the f(XIN) oscillation stabilizing wait time. Note: In the 7470/7477 group, the f(XCIN) is not available. 2 Interrupt processing after recovery After recovery from the stop mode, the interrupt request bit of timer 3 and timer 4 is "1." Clear it to "0" if necessary. The interrupt request bit of timer 1 and timer 2 may also be set to "1." Clear it to "0" as required.
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1.17.4 Related register (1) CPU mode register (Address 00FB16) The CPU mode register consists of a stack page selection bit+1 and system clock control bits +2. +1: In series having a RAM capacity of 192 bytes or less, this bit is not used because no RAM is located on page 1. (Be sure to set this bit to "0.") +2: In the 7470/7477 group, which is not provided with a sub-clock generating circuit, this bit is not used. (Be sure to set this bit to "0.") Figure 1.17.6 shows a structure of CPU mode register.
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
00
CPU mode register (CPUM) [Address 00FB16] Name 0, 1 Fix these bits to "0." 2 Stack page selection bit B Function At reset R W 0 0: In page 0 area 1: In page 1 area (Note 1) 0
3 4 5
Nothing is allocated for this bit. This is write enabled bit and is undefined at reading. P50, P51/XCIN,XCOUT selection bit XCOUT drive capacity selection bit 0: P50, P51 1: XCIN, XCOUT (Note 2) 0: Low 1: High (Note 2)
? 0 0 0
?!
6 Main clock (XIN-XOUT) 0: Oscillates stop bit 1: Stops (Note 2) 7 Internal system clock selection bit 0: XIN-XOUT selected (Ordinary mode) 1: XCIN-XCOUT selected (Low speed mode) (Note 2)
0
Notes 1: In the products having a RAM capacity of 192 bytes or less, set this bit to "0." 2: Since the 7470/7477 group is not provided with the sub-clock generating circuit, f(XCIN) cannot be used. Fix these bits to "0."
Fig. 1.17.6 Structure of CPU mode register
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1.18 State transitions
1.18 State transitions
The operation modes of the 7470/7471/7477/7478 group are classified as follows. q q q q q q Reset Oridinary mode Low-speed mode (7471/7478 group) Sub-clock mode (7471/7478 group) Stop mode Wait mode
Figure 1.18.1 shows a state transitions.
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1.18 State transitions
Reset
Wait mode State E Internal clock : Stopped
f(XIN): Oscillating f(XCIN): Stopped
Stop mode Ordinary mode State F WIT State A STP b7 b6 b5 b4 instruction instruction CPUM 0 0 0 0 Internal clock : Stopped f(XIN): Stopped Internal clock : f(XIN)/2 Interrupt
f(XIN): Oscillating f(XCIN): Stopped f(XCIN): Stopped
Interrupt (Note 1)
WIT instruction Internal clock : Stopped
f(XIN): Oscillating f(XCIN): Oscillating
Ordinary mode State B STP b7 b6 b5 b4 instruction CPUM 0 0 -- 1 Internal clock : Stopped f(XIN): Stopped Internal clock : f(XIN)/2
f(XIN): Oscillating f(XCIN): Oscillating f(XCIN): Stopped
Interrupt
Interrupt (Note 1)
(Note 2)
(Note 3) STP instruction Internal clock : Stopped
f(XIN): Stopped f(XCIN): Stopped
Internal clock : Stopped
f(XIN): Oscillating f(XCIN): Oscillating
Low-speed mode WIT (Note 4) State C instruction b7 b6 b5 b4
CPUM 1 0 -- 1
Internal clock : f(XCIN)/2 Interrupt
f(XIN): Oscillating f(XCIN): Oscillating
Interrupt (Note 1)
(Note 3) Sub-clock mode State G Internal clock : Stopped
f(XIN): Stopped f(XCIN): Oscillating
Low-speed mode WIT (Note 4) State D b7 b6 b5 b4 instruction
CPUM 1 1 -- 1
STP instruction Internal clock : Stopped
f(XIN): Stopped f(XCIN): Stopped
Internal clock : f(XCIN)/2 Interrupt
f(XIN): Stopped f(XCIN): Oscillating
Interrupt (Note 1)
Fig. 1.18.1 State transitions
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1.18 State transitions
Notes 1: When changing from the stop mode to another mode, oscillation stabilizing wait time is generated automatically by connecting timer 3 and timer 4. 2: In the 7471/7478 group, where oscillating the stopped clock and switching the system clock, it is necessary to wait at software until oscillation is stabilized. At this time, set the bit 5 of the CPU mode register to "1" and set the XCOUT drive capacity to the high power mode. After the oscillation of sub-clock f(XCIN) becomes stable, clear the bit to "0" (low power mode) as required. 3: In the 7471/7478 group, when returning from the low-speed mode to the ordinary mode, use the main clock f(XIN) as a count source of the internal clock (state B). After that, clear bit 4 of the CPU mode register to "0" to stop the oscillation of f(XCIN) if necessary. 4: When using the low-speed mode in the 7471/7478 group, use it in one of the following states. q Fix the XCOUT drive capacity to the high power mode (set the XCOUT drive capacity selection bit of the CPU register to "1.") q When fixing the XCOUT drive capacity to the low power mode (clear the XCOUT drive capacity selection bit of the CPU mode register to "0"), lower the value of the resistor Rd+ in the subclock oscillation circuit to a level at which the oscillation of f(XCIN) does not stop. + "Resistor Rd": Refer to the circuit example in "Chapter 2 Application, 2.7 Oscillation circuit."
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1.18 State transitions
2 Reset Ordinary mode (State A) Immediately after reset, the main clock divided by 2 (f(XIN)/2) is selected as an internal clock and the I/O pins XCIN and XCOUT of the sub-clock f(XCIN) become ordinary ports. "FF16" and "0716" are set in timer 3 and timer 4 respectively, and also the main clock divided by 16 (f(XIN)/16) is selected as a count source of timer 3 and the overflow signal of timer 3 is selected as a count source of timer 4. Then a down-count is started. When timer 4 overflows, the internal reset is released and the program starts from the address specified by reset vector. 2 Low-speed mode (Stae C and state D) To the low-speed mode (state C and state D) using the sub-clock divided by 2 (f(XCIN)/2) as an internal clock , a transition is made by way of the ordinary mode (state A) state B ( state C). In the 7470/7477 group, which is not provided with a sub-clock oscillation circuit, this mode is not provided. 2 Wait mode (State E) In this mode, all the states of registers, I/O ports and internal RAMs are held. The internal clock stops at "H" but the oscillator does not stop. From any of state A, state B, state C and state D, a return is made to the wait mode by executing the WIT instruction. When a return is made from the state D to the wait mode, the sub-clock mode in which only the timer function operates is provided. (In the 7470/7477 group, which is not provided with a sub-clock oscillation circuit, the sub-clock mode is not provided.) Refer to "1.17.2 Wait mode." 2 Stop mode (State F) In this mode, all the states of registers, I/O ports and internal RAMs except timer 3 and timer 4 are held and the oscillation of both main sub-clock is stopped. From any of state A, B, C and D, a return is made to the stop mode by executing the STP instruction. Refer to "1.17.1 Stop mode." 2 Sub-clock mode (State G) Only the clock-function is made to operate by sub-clock mode at low-power dissipation. The sub-clock mode (state G) is provided by executing the WIT instruction in the low-speed mode (state D), and restoration from this state to the low-speed mode is attached by each interrupt. In the 7470/7477 group, which is not provided with a sub-clock oscillation circuit, this mode is not provided.
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1.19 Built-in PROM version
1.19 Built-in PROM version
In contrast with the mask ROM version, a microcomputer incorporating a programmable ROM is called built-in PROM version. There are two types of built-in PROM version as shown below. q One Time PROM version Writing to the built-in PROM can be performed only once. Neither erase nor rewrite operations are enabled. q Built-in EPROM version The built-in EPROM version is a programmable microcomputer with window and can perform write, erase, and rewrite operations. The built-in PROM version has the EPROM mode for writing to the built-in PROM in addition to the same functions as those of the mask ROM version. For an outline of performance, a pin configuration and a functional block diagram of the built-in PROM version, refer to "1.3 Performance overview", "1.4 Pin configuration", and "1.6 Functional block diagram", respectively. The 7470/7471/7477/7478 group supports the built-in PROM versions shown in Table 1.19.1. Table 1.19.1 7470/7471/7477/7478 group built-in PROM version supporting products Product name M37470E4-XXXSP M37470E8-XXXSP M37471E4-XXXSP M37471E4-XXXFP M37471E8-XXXSP M37471E8-XXXFP M37471E8SS M37477E8-XXXSP M37477E8-XXXFP M37477E8TXXXSP M37477E8TXXXFP M37478E8-XXXSP M37478E8-XXXFP M37478E8TXXXSP M37478E8TXXXFP M37478E8SS (P)ROM size RAM size (bytes) (bytes) 8192 16384 8192 16384 192 384 192 384 I/O Ports Package Remarks
I/O ports: 22 (Including 4 analog 32P4B input pins.) Input ports: 4 42P4B I/O ports: 28 56P6N-A (Including 8 analog 42P4B input pins.) 56P6N-A Input ports: 8 42S1B-A 32P4B I/O ports: 18 Input ports: 8 32P2W-A (Including 4 analog 32P4B input pins.) 32P2W-A 42P4B I/O ports: 20 56P6N-A Input ports: 16 42P4B (Including 8 analog 56P6N-A input pins.) 42S1B-A
One Time PROM version
One Time PROM version EPROM version One Time PROM version One Time PROM version* One Time PROM version One Time PROM version* EPROM version (As of July, 1996)
16384
384
16384
384
*: Extended operating temperature version.
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1.19 Built-in PROM version
1.19.1 EPROM mode The built-in PROM version has the EPROM mode in addition to the same operation modes as those of the mask ROM version. The EPROM mode permits writing to the built-in PROM and reading from the builtin PROM. To the built-in PROM, writing, reading and erasing can be performed by the same operations as those of the M5M27C256K. Table 1.19.2 shows a pin function in EPROM mode and Figure 1.19.1 to 1.19.6 show a connections in EPROM mode. Table 1.19.2 Pin functions in EPROM mode Built-in PROM version VCC P33 VSS P11 to P17, P20 to P23, Pin name P30, P31, P40, P41 P00 to P07 VREF P32
M5M27C256K VCC VPP VSS A0 to A14 D0 to D7
CE OE
(TOP VIEW)
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CE
VSS
P17/SRDY P16/CLK P15/SOUT P14/SIN P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4
32 31 30 29
5 6 7 8 9 10 11 12 13 14 15 16
28 27 26 25 24 23 22 21 20 19 18 17
P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0 RESET VCC
D7 D6 D5 D4 D3 D2 D1 D0 A14 A13 VPP OE A12 A11 VCC
Outline 32P4B : Same functions as M5M27C256K
Fig. 1.19.1 Pin connection in EPROM mode of 7470 group
M37470E4-XXXSP M37470E8-XXXSP
VSS
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(TOP VIEW)
P53 P17/SRDY P16/CLK P15/SOUT P14/SIN P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
A10 A9 A8 A7 A6 A5 A4
A3 A2 A1 A0 CE
VSS
P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0 RESET P51/XCOUT P50/XCIN VCC
D7 D6 D5 D4 D3 D2 D1 D0
Outline 42P4B (Note) 42S1B-A (M37471E8SS) : Same functions as M5M27C256K Note: The only difference between the 42P4B package product and the 56P6N-A package product are package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AV SS pin.
Fig. 1.19.2 Pin connection in EPROM mode of 7471 group (1)
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M37471E4-XXXSP M37471E8-XXXSP M37471E8SS
A14 A13 VPP OE A12 A11
VSS VCC
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(TOP VIEW)
VPP OE A12
32 31
A14
A13
43
44
39
40
36
35
41
37
33
42
D5 D6 D7
VSS A10 A9 A8
NC P05 P06 P07 P52 NC VSS P53 P17/SRDY P16/CLK P15/SOUT NC
38
34
30
29
NC P04 P03 P02 P01 P00 P43 P42 P41 P40 NC P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0 NC
A11
D4
D3
D2
D1
D0
45 46 47 48 49 50 51 52 53 54 55 56
10 13 14 12 11 15 16 1 5 3 4 2 6 7 8 9
28 27 26 25 24
M37471E4-XXXFP M37471E8-XXXFP
23 22 21 20 19 18 17
RESET NC P51/XCOUT P50/XCIN NC VCC VSS AVSS NC XOUT XIN NC
VSS
VCC VSS
Outline 56P6N-A (Note)
NC: No connection : Same functions as M5M27C256K Note: The only difference between the 42P4B package product and the 56P6N-A package product are package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AVSS pin.
Fig. 1.19.3 Pin connection in EPROM mode of 7471 group (2)
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CE
A6
A7
A1
A0
A4
A5
A3
A2
NC P14/SIN P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF NC
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1.19 Built-in PROM version
(TOP VIEW)
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CE
VSS
P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4
32 31 30 29
5 6 7 8 9 10 11 12 13 14 15 16
28 27 26 25 24 23 22 21 20 19 18 17
P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0 RESET VCC
D7 D6 D5 D4 D3 D2 D1 D0 A14 A13 VPP OE A12 A11 VCC
Outline 32P4B (Note)
M37477E8-XXXSP M37477E8TXXXSP
VSS
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CE
VSS
P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4
32 31 30 29
5 6 7 8 9 10 11 12 13 14 15 16
28 27 26 25 24 23 22 21 20 19 18 17
P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0 RESET VCC
D7 D6 D5 D4 D3 D2 D1 D0 A14 A13 VPP OE A12 A11 VCC
Outline 32P2W-A (Note)
M37477E8-XXXFP M37477E8TXXXFP
VSS
: Same functions as M5M27C256K Note: The only difference between the 32P2W-A package product and the 32P4B package product are package shape, absolute maximum ratings.
Fig. 1.19.4 Pin connection in EPROM mode of 7477 group
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(TOP VIEW)
A10 A9 A8 A7 A6 A5 A4
A3 A2 A1 A0 CE
VSS
P53 P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0 RESET P51/XCOUT P50/XCIN VCC
D7 D6 D5 D4 D3 D2 D1 D0
Outline 42P4B (Note) 42S1B-A (M37478E8SS) NC: No connection : Same functions as M5M27C256K Note: The only difference between the 42P4B package product and the 56P6N-A package product are package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AV SS pin.
Fig. 1.19.5 Pin connection in EPROM mode of 7478 group (1)
M37478E8-XXXSP M37478E8TXXXSP M37478E8SS
A14 A13 VPP OE A12 A11
VSS VCC
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1.19 Built-in PROM version
(TOP VIEW)
VPP OE A12
32 31
A14
A13
43
44
39
40
36
35
41
37
33
42
D5 D6 D7
VSS A10 A9 A8
NC P05 P06 P07 P52 NC VSS P53 P17/SRDY P16/SCLK P15/TXD NC
38
34
30
29
NC P04 P03 P02 P01 P00 P43 P42 P41 P40 NC P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0 NC
A11
D4
D3
D2
D1
D0
45 46 47 48 49 50 51 52 53 54 55 56
10 13 14 12 11 15 16 1 5 3 4 2 6 7 8 9
28 27 26 25 24
M37478E8-XXXFP M37478E8TXXXFP
23 22 21 20 19 18 17
RESET NC P51/XCOUT P50/XCIN NC VCC VSS AVSS NC XOUT XIN NC
VSS
VCC VSS
Outline 56P6N-A (Note)
NC: No connection : Same functions as M5M27C256K Note: The only difference between the 42P4B package product and the 56P6N-A package product are package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AVSS pin.
Fig. 1.19.6 Pin connection in EPROM mode of 7478 group (2)
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CE
A6
A7
A1
A0
A4
A5
A3
A2
NC P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF NC
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1.19.2 Pin description Table 1.19.3 to Table 1.19.5 show the description of pin functions in the ordinary mode and the EPROM mode. Table 1.19.3 Pin description (1) Pin VCC, VSS Mode Ordinary /EPROM Name Power source Input/ Output Functions * Apply the following voltage to the VCC pin: 2.7 V to 4.5 V (at f(XIN) = (2.2 VCC-2) MHz) or 4.5 V to 5.5 V (at f(XIN) = 8 MHz). * Apply 0 V to the VSS pin. * Ground level input pin for the A-D converter. * Apply the same voltage as the VSS pin to the AVSS pin. Note: This pin is dedicated to 56P6N-A package products among the 7471/7478 group. * Reference voltage input pin for the A-D converter. * When using the A-D converter, apply VCC/2 (Q2) to VCC [V]. * When not using the A-D converter, connect to VCC. * VREF works as CE input. * Reset input pin * The microcomputer is put into a reset state by keeping the RESET pin at "L" for 2 ms or more, and the reset state is released by returning the RESET pin to "H." * Connect to the VSS pin. * An input pin and an output pin for the main clock generating circuit. * Connect a ceramic resonator or a quartz-crystal oscillator between pins XIN and XOUT. * A feedback resistor is incorporated between the XIN and the XOUT pins. * To use an external clock input, connect the clock oscillation source to the XIN pin and leave the XOUT pin open. * Port P0 is an 8-bit I/O port. * The output structure is CMOS output. * In input mode, a pull-up transistor is connectable in units of one bit. * In input mode, a key-on wake up function is provided. * Port P0 works as data I/O (D0 - D7)
AVSS
Ordinary /EPROM
Analog power source
VREF
Ordinary
Reference voltage input
Input
RESET
EPROM Ordinary
Mode input Reset input
Input Input
XIN
EPROM Ordinary /EPROM
Reset input Clock input
Input Input
XOUT
Ordinary /EPROM
Clock output
Output
P00-P07
Ordinary
I/O port P0
Input/ output
EPROM
Data I/O D0-D7
Input/ output
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1.19 Built-in PROM version
Table 1.19.4 Pin description (2) Pin P10-P17 Mode Ordinary Name I/O port P1 Input/ Output Input/ output Functions * Port P1 is an 8-bit I/O port. * The output structure is CMOS output. * In input mode, pull-up transistor can be connected in units of 4-bit. * Pins P12 and P13 are in common with timer output pins T0, T1 respectively. * In the case of the 7470/7471 group, P14 - P17 are in common with serial I/O pins SIN, SOUT, CLK, SRDY respectively. * In the case of the 7470/7471 group, the outputs of pins SOUT and the SRDY can be N-channel open drain outputs. * In the case of the 7477/7478 group, pins P14 - P17 are in common with serial I/O pins RXD, TXD, SCLK, SRDY, respectively. * The P11-P17 pins are address (A4 - A10) input pins. Put P10 into the open state. * Port P2 is an 8-bit I/O port. * The output structure is CMOS output. * In input mode, pull-up transistor can be connected in units of 4-bit. * Pins P20-P27 are in common with analog input pins IN0-IN7 respectively. Note: The 7470 group has only the 4 pins P20-P23 (IN0-IN3). * Port P2 is an 8-bit input port. * It is impossible to connect a pull-up transistor. * Pins P20-P27 are in common with analog input pins IN0-IN7 respectively. Note: The 7477 group has only the 4 pins P20-P23 (IN0-IN3) are available. * The P20 to P23 pins are address (A0-A3) input pins. * In the case of the 7471/7478 group, put the P24-P27 pins into the open state.
EPROM P20-P27 Ordinary
Address input A4-A10 I/O port P2 (7470/7471 group)
Input Input/ output
Input port P2 (7477/7478 group)
Input
EPROM
Address input A0-A3
Input
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Table 1.19.5 Pin description (3) Pin P30-P33 Mode Ordinary Name Input port P3 Input/ Output Input Functions * Port P3 is a 4-bit input port. * Pins P30, P31 are in common with external interrupt input pins INT0, INT1 respectively. * Pins P32, P33 are in common with timer input pins CNTR0, CNTR1 respectively. * The P30 and P31 pins are the address (A11, A12) input pins. * The P32 pin becomes an OE input pin. * The P33 pin is a VPP input pin and VPP is applied to it when the VPP is input and the program is verified. * Port P4 is a 4-bit I/O port. * The output structure is CMOS output. * In input mode, pull-up transistor can be connected in units of 4-bit. Note: The 7470/7477 group has only 2 pins P40 and P41. * The P40 to P41 pins are the address (A13, A14) input pins. * In the case of the 7471/7478 group, put the P42 and P43 pins into the open state. * Port P5 is a 4-bit input port. * Pull-up transistor can be connected in units of 4-bit. * Pins P50, P51 are in common with input/output pins for sub-clock generating circuit XCIN, XCOUT respectively. * When using pins P50 and P51 as pins XCIN and XCOUT, connect a quartz-crystal oscillator between pins XCIN and XCOUT. * When using pins P50 and P51 as pins XCIN and XCOUT, a feedback resistor is connected between pins XCIN and XCOUT. * To use an external clock input, connect the clock oscillation source to the XCIN pin and leave the XCOUT pin open. Note: Only the 7471/7478 group has pins P50 to P53. * Put this port into the open state.
EPROM
Address input A11, A12 Mode input VPP input
Input
P40-P43
Ordinary
I/O port P4
Input/ output
EPROM
Address input A13, A14
Input
P50-P53
Ordinary
Input port P5
Input
EPROM
Input port P5
Input
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1.19 Built-in PROM version
1.19.3 Writing, reading, and erasing to built-in PROM The built-in PROM version is put into the EPROM mode by applying the "L" level to the RESET pin. Write, read and erase operations to the built-in PROM in the EPROM mode are described below. Table 1.19.6 shows input signals in each mode. (1) Reading q Apply 0 V to the RESET pin and 5 V to the VCC pin. q When an address signal (A0-A14) is input and the CE pin and the OE pin are caused to go "L", the contents of the PROM appear to data I/O pins (D0-D7). q The data I/O pins (D0-D7) are put into a floating when either the CE pin or the OE pin is in the "H" state. (2) Writing q Apply 0 V to the RESET pin and 5 V to the VCC pin. q When the OE pin is caused to go to "H" and VPP is applied to the VPP pin, the program mode is provided. q Set an address to the address input pins (A0-A14) and give write data to the data I/O pins (D0-D7) in parallel. q In the above condition, a write operation is performed by causing the CE pin to go to "L". When using a PROM programmer, specify an address into the following area. q Address 600016 to address 7FFF16 (for the M3747xE4) q Address 400016 to address 7FFF16 (for the M3747xE8) (3) Erasing q An erase operation is enabled only in the built-in EPROM version with window (M37471E8SS/ M37478E8SS). q Data can be erased by irradiating ultraviolet rays having a wave length of 2537A. q The minimum amount of irradiation required for an erase operation is 15 W*s/cm2 . Table 1.19.6 Input/Output signal on each mode Pin CE OE VPP VCC RESET Mode Reading VIL VIL VCC Output disable VIL VIH VCC Writing VIL VIH VPP VCC 0V Writing verify VIH VIL VPP VIH VIH VPP Writing disable Note: VIL denotes an "L" input voltage and VIH denotes an "H" input voltage. D0 to D7 Output Floating Input Output Floating
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1.19 Built-in PROM version
1.19.4 Notes on use The notes on using the built-in PROM version are shown below. (1) All built-in PROM version products s Precautions at write operation q Be careful not to apply an overvoltage to pins because a high voltage is used for a write operation. Exercise special care when turning on the power supply. q For writing the contents of the PROM, use a dedicated programming adapter. This permits using a general-purpose PROM programmer for writing data. For details of dedicated programming adapters, refer to the "DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS" data book. s Precautions at read operation q When reading the contents of the PROM, use a dedicated programming adapter, so that reading can be performed by a general-purpose PROM programmer. For details of dedicated programming adapters, refer to the "DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS" data book.
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1.19 Built-in PROM version
(2) One Time PROM version s Precautions before use q The PROM of the One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 1.19.7 is recommended to verify programming.
Programming with PROM programmer
Screening (Caution) (Leave at 150C for 40 hours)
Verification with PROM programmer
Functional check in target device
Caution: The screening temperature is far higher than the storage temperature. Never expose to 150C exceeding 100 Hours.
Fig. 1.19.7 Programming and testing of One Time PROM version (3) Built-in EPROM version s Precautions on erasing q Sunlight and fluorescent light include light that may erase the information written in the built-in PROM. When using the built-in EPROM version in the read mode, be sure to cover the transparent glass portion with a seal. q This seal to cover the transparent glass portion is prepared on our side. Be careful not to bring the seal into contact with the microcomputer lead wires when covering the portion with the seal because this seal is made of metal (aluminum). q Before erasing data, clean the transparent glass. If any finger stain or seal adhesive is stuck to the transparent glass, this prevents ultraviolet rays from passing, thereby affecting the erase characteristic adversely.
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1.20 Emulator MCU
The M37471RSS and the M37478RSS are emulator MCUs for the 7470/7471/7477/7478 group software development. When an emulator is connected to the socket on the top surface, user program debugging can be performed efficiently by using a real-time trace function, etc. It is possible to monitor every internal bus information through the emulator because 16 address bus signals, two-way data bus signals and SYNC, RD, WR and f signals are output from the socket on the top surface. In the debug system using the M37471RSS and the M37478RSS, the MCU pins for emulator are directly connected to the user system. This permits debugging in a condition similar to a real mounting condition. For details of development support systems for the M37471RSS and the M37478RSS, refer to the "DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTER" data book. Figure 1.20.1 shows a pin connection diagram of the M37471RSS and M37478RSS.
PIN CONFIGURATION (TOP VIEW)
P53 P17/SRDY P16/CLK (Note 1) P15/SOUT P14/SIN P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 (Note 2) P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
1 2 3 4 5 6 7 8 9 10 11 12 13 14
42 41 40 39
CNVSS2 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0/RD D1/WR D2/SYNC VSS2
VCC2 A14 A13 A8 A9 A11 A10 S D7 D6 D5 D4/A15 D3/A14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
M37471RSS (Note 3) M37478RSS
Outline 42S1M
P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0 RESET P51/XCOUT P50/XCIN VCC
Notes 1: In the case of the M37478RSS, the pins CLK, SOUT, S IN shown in this figure function as the pins SCLK , TxD, RxD respectively. 2: In the case of the M37478RSS, the pins P20 /IN0-P27/IN7 shown in this figure function as the input pins. 3: The power source voltage of the M37471RSS and the M37478RSS is 5 V5 %.
Fig. 1.20.1 Pin configuration of M37471RSS and M37478RSS
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1.21 Electrical characteristics
1.21.1 Electrical characteristics (1) 7470 group electrical characteristics Table 1.21.1 shows the absolute maximum ratings of the 7470 group. Table 1.21.2 shows the recommended operating conditions. Table 1.21.3 shows the electrical characteristics. Table 1.21.4 shows the A-D converter characteristics. Table 1.21.1 Absolute maximum ratings (7470 group)
Symbol VCC VI VO Pd Topr Tstg Parameter Power source voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions All voltages are based on VSS. Output transistors are cut-off. Ta = 25 C Ratings -0.3 to +7 -0.3 to VCC+0.3 -0.3 to VCC+0.3 1000 -20 to +85 -40 to +150 Unit V V V mW C C
Table 1.21.2 Recommended operating conditions (7470 group)
(VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = -20 C to +85 C, unless otherwise noted)
Symbol VCC VSS VIH VIH VIH VIL VIL VIL VIL IOH(sum) IOH(sum) IOL(sum) IOL(sum) IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(CNTR) f(CLK) f(XIN) Power source voltage Parameter f(XIN) = 8.0 MHz f(XIN) = (2.2VCC-2.0 )MHz Min. 4.5 2.7 0.8VCC 0.7VCC 0.8VCC 0 0 0 0 Limits Typ. 5.0 0 VCC VCC VCC 0.2VCC 0.25VCC 0.16VCC 0.12VCC -30 -30 60 60 -10 20 -5 10 2 1 2 1 8 2.2VCC-2.0 Max. 5.5 4.5 Unit V V V V V V V V V V mA mA mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz
Power source voltage "H" input voltage P00 to P07, P10 to P17, P30 to P33 "H" input voltage P20 to P23, P40, P41 "H" input voltage XIN, RESET "L" input voltage P00 to P07, P10 to P17, P30 to P33 "L" input voltage P20 to P23, P40, P41 "L" input voltage XIN "L" input voltage RESET "H" sum output current of P00 to P07 and P40 and P41 "H" sum output current of P10 to P17 and P20 to P23 "L" sum output current of P00 to P07, P40 and P41 "L" sum output current of P10 to P17 and P20 to P23 "H" peak output current P00 to P07, P10 to P17, P20 to P23, P40, P41 "L" peak output current P00 to P07, P10 to P17, P20 to P23, P40, P41 "H" average output current P00 to P07, P10 to P17, P20 to P23, P40, P41 (Note 1) "L" average output current P00 to P07, P10 to P17, P20 to P23, P40, P41 (Note 1) Timer input frequency f(XIN) = 8 MHz CNTR0 (P32), f(XIN) = 4 MHz CNTR1 (P33) (Note 2) Serial I/O clock input frequency f(XIN) = 8 MHz f(XIN) = 4 MHz CLK (P16) (Note 2) Clock input oscillation frequency VCC = 4.5 V to 5.5 V VCC = 2.7 V to 4.5 V (Note 2)
Notes
1: The average output current IOH (avg) or IOL (avg) are the average value during a 100 ms. 2: The oscillation frequency is at 50 % duty cycle.
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1.21 Electrical characteristics
Table 1.21.3 Electrical characteristics (7470 group)
(VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = -20 C to +85 C, unless otherwise noted)
Symbol VOH Parameter "H" output voltage P00 to P07, P10 to P17 P20 to P23, P40, P41 "L" output voltage P00 to P07, P10 to P17 P20 to P23, P40, P41 Hysteresis P00 to P07 P30 to P33 Hysteresis RESET Hysteresis P14/SIN P16/CLK "L" input current P00 to P07, P10 to P17 P30 to P32, P40, P41 "L" input current P33 "L" input current P20 to P23 "L" input current XIN, RESET "H" input current P00 to P07, P10 to P17 P30 to P32, P40, P41 "H" input current P33 "H" input current P20 to P23 "H" input current XIN, RESET Test conditions VCC = 5 V, IOH = -5 mA VCC = 3 V, IOH = -1.5 mA VCC = 5 V, IOL = 10 mA VCC = 3 V, IOL = 3 mA VCC VCC VCC VCC = = = = 5 3 5 3 V V V V = = = = = = = = = = = = = = 5 3 5 3 5 3 5 3 5 3 5 3 5 3 V V V V V V V V V V V V V V 0.5 0.3 0.5 0.3 0.5 0.3 -5 -3 -1.0 -0.35 -5 -3 -5 -3 -1.0 -0.35 -5 -3 5 3 5 3 5 3 5 3 14 7 3.6 15 8 4 4 2 1 1 10 5.5 Min. 3.0 2.0 2.0 1.0 Limits Typ. Max. Unit V V V V V V V V V V A A mA mA A A A A mA mA A A
A A A A A A A A mA mA mA mA mA mA mA mA mA A A V
VOL VT+ - VT- VT+ - VT- VT+ - VT-
IIL
IIL
IIL
IIL IIH IIH IIH IIH
VCC VCC VI = 0 V VCC Not use pull-up transistor VCC VI = 0 V VCC Use pull-up transistor VCC VCC VI = 0 V VCC VI = 0 V, not use pull-up tran- VCC sistor, not use as analog input VCC VI = 0 V, use pull-up transistor, VCC not use as analog input VCC VCC VI = 0 V XIN is at stop mode VCC Use as SIN or CLK VI = VCC Not use pull-up transistor VI = VCC
-0.25 -0.08
-0.5 -0.18
-0.25 -0.08
-0.5 -0.18
VCC = 5 V VCC = 3 V V V V V V V V V V V V V C C 2.0 7 3.5 1.8 7.5 4 2 2 1 0.5 0.1 1
ICC
Power source current
VRAM
RAM retention voltage
VCC = 5 VCC = 3 VI = VCC, not use pull-up tran- VCC = 5 sistor, not use as analog input VCC = 3 VCC = 5 VI = VCC VCC = 3 XIN is at stop mode At system op- f(XIN) = 8 MHz VCC = 5 eration, A-D conversion is not executed f(XIN) = 4 MHz VCC = 3 At system op- f(XIN) = 8 MHz VCC = 5 eration, A-D conversion f(XIN) = 4 MHz is executed VCC = 3 f(XIN) = 8 MHz VCC = 5 At wait mode f(XIN) = 4 MHz VCC = 3 Ta = 25 At stop mode VCC = 5 V Ta = 85 Stop all oscillation
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Table 1.21.4 A-D converter characteristics (7470 group) (VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = -20 C to +85 C, f(XIN) = 4 MHz, unless otherwise noted)
Symbol -- -- -- VOT VFST TCONV VREF RLADDER VIA Parameter Resolution Non-linearity error Differential non-linearity error Zero transition error Full scale transition error Conversion time Reference input voltage Ladder resistance value Analog supply voltage VCC = VREF = 5.12 V, IOL(sum) = 0 VCC = VREF = 3.072 V, IOL(sum) = 0 VCC = VREF = 5.12 V VCC = VREF = 3.072 V f(XIN) = f(XIN) = mA mA Test conditions Min. Limits Typ. Max. 8 2 0.9 2 3 4 7 12.5 25 VCC 5 10 VREF Unit bits LSB LSB LSB LSB LSB LSB s s V k V
8 MHz 4 MHz 0.5VCC (Note) 2 0
Note: Set the VREF voltage to 0.5 VCC or more and 2 V or more. When using no A-D converter, connect it to VCC.
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1.21 Electrical characteristics
(2) 7471 group electrical characteristics Table 1.21.5 shows the absolute maximum ratings of the 7471 group. Table 1.21.6 shows the recommended operating conditions. Table 1.21.7 shows the electrical characteristics. Table 1.21.8 shows the A-D converter characteristics. Table 1.21.5 Absolute maximum ratings (7471 group)
Symbol VCC VI VO Pd Topr Tstg Parameter Power source voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions All voltages are based on VSS. Output transistors are cut-off. Ta = 25 C Ratings -0.3 to +7 -0.3 to VCC+0.3 -0.3 to VCC+0.3 1000 (Note) -20 to +85 -40 to +150 Unit V V V mW C C
Note: The rating is 500 mW for the 56P6N-A package product. Table 1.21.6 Recommended operating conditions (7471 group) (VCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = -20 C to +85 C, unless otherwise noted)
Symbol VCC VSS AVSS VIH VIH VIH VIL VIL VIL VIL IOH(sum) IOH(sum) IOL(sum) IOL(sum) IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(CNTR) f(CLK) f(XIN) f(XCIN) Power source voltage Parameter f(XIN) = 8.0 MHz f(XIN) = (2.2VCC-2.0) MHz Min. 4.5 2.7 Limits Typ. 5.0 0 0 0.8VCC 0.7VCC 0.8VCC 0 0 0 0 VCC VCC VCC 0.2VCC 0.25VCC 0.16VCC 0.12VCC -30 -30 60 60 -10 20 -5 10 2 1 2 1 8 2.2VCC-2.0 50 Max. 5.5 4.5 Unit V V V V V V V V V V V mA mA mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz kHz
Power source voltage Analog supply voltage "H" input voltage P00 to P07, P10 to P17, P30 to P33 "H" input voltage P20 to P27, P40 to P43, P50 to P53 (Note 1) "H" input voltage XIN, RESET "L" input voltage P00 to P07, P10 to P17, P30 to P33 "L" input voltage P20 to P27, P40 to P43, P50 to P53 (Note 1) "L" input voltage XIN "L" input voltage RESET "H" sum output current of P00 to P07 and P40 to P43 "H" sum output current of P10 to P17 and P20 to P27 "L" sum output current of P00 to P07 and P40 to P43 "L" sum output current of P10 to P17 and P20 to P27 "H" peak output current P00 to P07, P10 to P17, P20 to P27, P40 to P43 "L" peak output current P00 to P07, P10 to P17, P20 to P27, P40 to P43 "H" average output current P00 to P07, P10 to P17, P20 to P27, P40 to P43 (Note 2) "L" average output current P00 to P07, P10 to P17, P20 to P27, P40 to P43 (Note 2) Timer input frequency f(XIN) = 8 MHz CNTR0 (P32) f(XIN) = 4 MHz CNTR1 (P33) (Note 3) Serial I/O clock input frequency f(XIN) = 8 MHz CLK (P16) (Note 3) f(XIN) = 4 MHz Clock input oscillation frequency VCC = 4.5 V to 5.5 V (Note 3) VCC = 2.7 V to 4.5 V Sub-clock input oscillation frequency (Note 3, 4)
32
Notes 1: 2: 3: 4:
Except when P50 is used as XCIN. The average output current IOH(avg) or IOL(avg) are the average value during a 100 ms. The oscillation frequency is at 50 % duty cycle. Set f(XCIN) < f(XIN)/3 when the sub-clock is used.
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Table 1.21.7 Electrical characteristics (7471 group)
(VCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = -20 C to +85 C, unless otherwise noted)
Symbol VOH Parameter "H" output voltage P00 to P07, P10 to P17 P20 to P27, P40 to P43 "L" output voltage P00 to P07, P10 to P17 P20 to P27, P40 to P43 Hysteresis P00 to P07 P30 to P33 Hysteresis RESET Hysteresis P14/SIN P16/CLK "L" input current P00 to P07, P10 to P17 P30 to P32, P40 to P43 P50 to P53 "L" input current P33 "L" input current P20 to P27 "L" input current XIN, RESET "H" input current P00 to P07, P10 to P17 P30 to P32, P40 to P43 P50 to P53 "H" input current P33 "H" input current P20 to P27 "H" input current XIN, RESET Test conditions VCC = 5 V, IOH = -5 mA VCC = 3 V, IOH = -1.5 mA VCC = 5 V, IOL = 10 mA VCC = 3 V, IOL = 3 mA VCC VCC VCC VCC = = = = 5 3 5 3 V V V V VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC = = = = = = = = = = = = = = 5 3 5 3 5 3 5 3 5 3 5 3 5 3 V V V V V V V V V V V V V V 0.5 0.3 0.5 0.3 0.5 0.3 -5 -3 -1.0 -0.35 -5 -3 -5 -3 -1.0 -0.35 -5 -3 5 3 5 3 5 3 5 3 14 7 3.6 15 8 4 80 40 4 2 1 12 8 1 10 5.5 Min. 3.0 2.0 2.0 1.0 Limits Typ. Max. Unit V V V V V V V V V V A A mA mA A A A A mA mA A A
A A A A A A A A mA mA mA mA mA mA A A
VOL VT+ - VT- VT+ - VT- VT+ - VT-
When used as SIN or CLK VI = 0 V Not use pull-up transistor VI = 0 V Use pull-up transistor VI = 0V VI = 0 V, not use pull-up transistor, not use as analog input VI = 0 V, use pull-up transistor, not use as analog input VI = 0 V XIN is at stop mode VI = VCC Not use pull-up transistor VI = VCC
IIL
-0.25 -0.08
-0.5 -0.18
IIL
IIL
-0.25 -0.08
-0.5 -0.18
IIL
VCC = 5 V VCC = 3 V V V V V V V V V V V V V V V V V C C 2.0 7 3.5 1.8 7.5 4 2 30 15 2 1 0.5 3 2 0.1 1
IIH
IIH IIH IIH
ICC
Power source current
VRAM
RAM retention voltage
VCC = 5 VCC = 3 VI = VCC, not use pull-up tran- VCC = 5 sistor, not use as analog input VCC = 3 VCC = 5 VI = VCC VCC = 3 XIN is at stop mode At system op- f(XIN) = 8 MHz eration, VCC = 5 A-D conversion is not executed f(XIN) = 4 MHz VCC = 3 At system op- f(XIN) = 8 MHz VCC = 5 eration, A-D conversion f(XIN) = 4 MHz is executed VCC = 3 In low-speed mode, Ta = 25C, low-power mode VCC = 5 f(XCIN) = 32 kHz At A-D conversion is not executed VCC = 3 f(XIN) = 8 MHz VCC = 5 At wait mode f(XIN) = 4 MHz VCC = 3 At wait mode, Ta = 25C, VCC = 5 low-power mode, f(XCIN) = VCC = 3 32 kHz Ta = 25 At stop mode, VCC = 5 V Ta = 85 Stop all oscillation
mA mA mA
A A A A V
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1.21 Electrical characteristics
Table 1.21.8 A-D converter characteristics (7471 group) (VCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = -20 C to +85 C, f(XIN) = 4 MHz, unless otherwise noted)
Symbol -- -- -- VOT VFST TCONV VREF RLADDER VIA Parameter Resolution Non-linearity error Differential non-linearity error Zero transition error Full scale transition error Conversion time Reference input voltage Ladder resistance value Analog input voltage VCC = VREF = 5.12 V, IOL(sum) = 0 VCC = VREF = 3.072 V, IOL(sum) = 0 V = VREF = 5.12 V VCC = VREF = 3.072 V f(XIN) = f(XIN) = mA mA Test conditions Min. Limits Typ. Max. 8 2 0.9 2 3 4 7 12.5 25 VCC 5 10 VREF Unit bits LSB LSB LSB LSB LSB LSB s s V k V
8 MHz 4 MHz 0.5VCC (Note) 2 0
Note: Set the VREF voltage to 0.5 VCC or more and 2 V or more. When using no A-D converter, connect it to VCC.
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(3) 7477 group electrical characteristics Table 1.21.9 shows the absolute maximum ratings of the 7477 group. Table 1.21.10 shows the recommended operating conditions. Table 1.21.11 shows the electrical characteristics. Table 1.21.12 shows the A-D converter characteristics. Table 1.21.9 Absolute maximum ratings (7477group)
Symbol VCC VI VO Pd Topr Tstg Parameter Power source voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions All voltages are based on VSS. Output transistors are cut-off. Ta = 25 C Ratings -0.3 to +7 -0.3 to VCC+0.3 -0.3 to VCC+0.3 1000 (Note 1) -20 to +85 (Note 2) -40 to +150 (Note 3) Unit V V V mW C C
Notes 1: The rating is 500 mW for the 32P2W-A package product. 2: -40 C to +85 C for extended operating temperature version. 3: -65 C to +150 C for extended operating temperature version. Table 1.21.10 Recommended operating conditions (7477 group) (VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = -20 C to +85 C(Note 1), unless otherwise noted)
Symbol VCC VSS VIH VIH VIH VIL VIL VIL VIL IOH(sum) IOH(sum) IOL(sum) IOL(sum) IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(CNTR) Power source voltage Parameter f(XIN) = 8.0 MHz f(XIN) = (2.2VCC-2.0) MHz Min. 4.5 2.7 0.8VCC 0.7VCC 0.8VCC 0 0 0 0 Limits Typ. 5.0 0 VCC VCC VCC 0.2VCC 0.25VCC 0.16VCC 0.12VCC -30 -30 60 60 -10 20 -5 10 2 1 500 250 2 1 8 2.2VCC-2.0 Max. 5.5 4.5 Unit V V V V V V V V V V mA mA mA mA mA mA mA mA MHz MHz kHz kHz MHz MHz MHz MHz
f(SCLK)
f(XIN)
Power source voltage "H" input voltage P00 to P07, P10 to P17, P30 to P33 "H" input voltage P20 to P23, P40, P41 "H" input voltage XIN, RESET "L" input voltage P00 to P07, P10 to P17, P30 to P33 "L" input voltage P20 to P23, P40, P41 "L" input voltage XIN "L" input voltage RESET "H" sum output current P00 to P07, P40 and P41 "H" sum output current P10 to P17 "L" sum output current P00 to P07, P40 and P41 "L" sum output current P10 to P17 "H" peak output current P00 to P07, P10 to P17, P40, P41 "L" peak output current P00 to P07, P10 to P17, P40, P41 "H" average output current P00 to P07, P10 to P17, P40, P41 (Note 2) "L" average output current P00 to P07, P10 to P17, P40, P41 (Note 2) Timer input frequency f(XIN) = 8 MHz CNTR0 (P32), CNTR1 (P33) (Note 3) f(XIN) = 4 MHz Use as clock synchro- f(XIN) Serial I/O clock input frequency nous serial I/O mode f(XIN) SCLK (P16) (Note 3) Use as UART f(XIN) mode f(XIN) Clock input oscillation frequency VCC = 4.5 V to 5.5 V (Note 3) VCC = 2.7 V to 4.5 V
= = = =
8 4 8 4
MHz MHz MHz MHz
Notes 1: -40 C to +85 C for extended operating temperature version. 2: The average output current IOH (avg) or IOL (avg) are the average value during a 100 ms. 3: The oscillation frequency is at 50 % duty cycle.
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Table 1.21.11 Electrical characteristics (7477 group)
(VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = -20 C to +85 C(Note), unless otherwise noted)
Symbol VOH Parameter "H" output voltage P00 to P07, P10 to P17 P40, P41 "L" output voltage P00 to P07, P10 to P17 P40, P41 Hysteresis P00 to P07 P30 to P33 Hysteresis RESET Hysteresis P14/RxD P16/SCLK "L" input current P00 to P07, P10 to P17 P30 to P32, P40, P41 "L" input current P33 "L" input current P20 to P23 "L" input current XIN, RESET "H" input current P00 to P07, P10 to P17 P30 to P32, P40, P41 "H" input current P33 "H" input current P20 to P23 "H" input current XIN, RESET Test conditions VCC = 5 V, IOH = -5 mA VCC = 3 V, IOH = -1.5 mA VCC = 5 V, IOL = 10 mA VCC = 3 V, IOL = 3 mA VCC VCC VCC VCC = = = = 5 3 5 3 V V V V VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC = = = = = = = = = = = = 5 3 5 3 5 3 5 3 5 3 5 3 V V V V V V V V V V V V 0.5 0.3 0.5 0.3 0.5 0.3 -5 -3 -1.0 -0.35 -5 -3 -5 -3 -5 -3 5 3 5 3 5 3 5 3 14 7 3.6 15 8 4 4 2 1 1 10 5.5 Min. 3.0 2.0 2.0 1.0 Limits Typ. Max. Unit V V V V V V V V V V A A mA mA A A A A A A
A A A A A A A A mA mA mA mA mA mA mA mA mA A A V
VOL VT+ - VT- VT+ - VT- VT+ - VT-
When used as RxD or SCLK VI = 0 V Not use pull-up transistor VI = 0 V Use pull-up transistor VI = 0V VI = 0 V, Not use as analog input VI = 0 V XIN is at stop mode VI = VCC Not use pull-up transistor VI = VCC VI = VCC Not use as analog input VI = VCC XIN is at stop mode At system op- f(XIN) = 8 MHz eration,
A-D conversion is not executed At system operation, A-D conversion is executed
IIL
-0.25 -0.08
-0.5 -0.18
IIL IIL IIL IIH IIH IIH IIH
VCC = 5 V VCC = 3 V VCC VCC VCC VCC VCC VCC = = = = = = 5 3 5 3 5 3 V V V V V V 7 3.5 1.8 7.5 4 2 2 1 0.5 0.1 1 2.0
VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V Ta = 25 C Ta = 85 C
f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz
ICC
Power source current
At wait mode
f(XIN) = 4 MHz
At stop mode, VCC = 5 V VRAM RAM retention voltage Stop all oscillation
Note: -40 C to +85 C for extended operating temperature version.
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Table 1.21.12 A-D converter characteristics (7477 group)
(VCC = 2.7 V to 5.5 V, VSS = 0 V, Ta = -20 C to +85 C(Note 1), unless otherwise noted)
Symbol -- -- TCONV VREF RLADDER VIA Parameter Resolution Absolute accuracy Conversion time Reference input voltage Ladder resistance value Analog input voltage VCC = 4.5 V to 5.5 V, f(XIN) = 8 MHz VCC = 2.7 V to 5.5 V, f(XIN) = 4 MHz 0.5VCC (Note 2) 2 0 Test conditions Min. Limits Typ. Max. 8 3 12.5 25 VCC 5 10 VREF Unit bits LSB s s V k V
Notes 1: -40 C to +85 C for extended operating temperature version. 2: Set the VREF voltage to 0.5 VCC or more and 2 V or more. When using no A-D converter, connect it to VCC.
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(4) 7478 group electrical characteristics Table 1.21.13 shows the absolute maximum ratings of the 7478 group. Table 1.21.14 shows the recommended operating conditions. Table 1.21.15 shows the electrical characteristics. Table 1.21.16 shows the A-D converter characteristics. Table 1.21.13 Absolute maximum ratings (7478 group)
Symbol VCC VI VO Pd Topr Tstg Parameter Power source voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions All voltages are based on VSS. Output transistors are cut-off. Ta = 25 C Ratings -0.3 to +7 -0.3 to VCC+0.3 -0.3 to VCC+0.3 1000 (Note 1) -20 to +85 (Note 2) -40 to +150 (Note 3) Unit V V V mW C C
Notes 1: The rating is 500 mW for the 56P6N-A package product. 2: -40 C to +85 C for extended operating temperature version. 3: -65 C to +150 C for extended operating temperature version. Table 1.21.14 Recommended operating conditions (7478 group) (VCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = -20 C to +85 C(Note 1), unless otherwise noted)
Symbol VCC VSS AVSS VIH VIH VIH VIL VIL VIL VIL IOH(sum) IOH(sum) IOL(sum) IOL(sum) IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(CNTR) Power source voltage Parameter f(XIN) = 8.0 MHz f(XIN) =(2.2VCC-2.0) MHz Min. 4.5 2.7 Limits Typ. 5.0 0 0 0.8VCC 0.7VCC 0.8VCC 0 0 0 0 VCC VCC VCC 0.2VCC 0.25VCC 0.16VCC 0.12VCC -30 -30 60 60 -10 20 -5 10 2 1 500 250 2 1 8 2.2VCC-2.0 50 Max. 5.5 4.5 Unit V V V V V V V V V V V mA mA mA mA mA mA mA mA MHz MHz kHz kHz MHz MHz MHz MHz kHz
f(SCLK)
f(XIN) f(XCIN)
Power source voltage Analog supply voltage "H" input voltage P00 to P07, P10 to P17, P30 to P33 "H" input voltage P20 to P27, P40 to P43, P50 to P53 (Note 2) "H" input voltage XIN, RESET "L" input voltage P00 to P07, P10 to P17, P30 to P33 "L" input voltage P20 to P27, P40 to P43, P50 to P53 (Note 2) "L" input voltage XIN "L" input voltage RESET "H" sum output current of P00 to P07 and P40 to P43 "H" sum output current of P10 to P17 "L" sum output current of P00 to P07 and P40 toP43 "L" sum output current of P10 to P17 "H" peak output current P00 to P07, P10 to P17, P40 to P43 "L" peak output current P00 to P07, P10 to P17, P40 to P43 "H" average output current P00 to P07, P10 to P17, P40 to P43 (Note 3) "L" average output current P00 to P07, P10 to P17, P40 to P43 (Note 3) Timer input frequency f(XIN) = 8 MHz CNTR0 (P32), CNTR1 (P33) (Note 4) f(XIN) = 4 MHz Use as clock synchro- f(XIN) = 8 MHz Serial I/O clock input frequency nous serial I/O mode f(XIN) = 4 MHz SCLK (P16) (Note 4) Use as UART f(XIN) = 8 MHz mode f(XIN) = 4 MHz Clock input oscillation frequency VCC = 4.5 V to 5.5 V (Note 4) VCC = 2.7 V to 4.5 V Sub-clock input oscillation frequency (Notes 4, 5)
32
Notes 1: 2: 3: 4: 5:
-40 C to +85 C for extended operating temperature version. Except when P50 is used as XCIN. The average output current IOH (avg) and IOL (avg) are the average value during a 100 ms. The oscillation frequency is at 50 % duty cycle. Set f(XCIN) < f(XIN)/3 when the sub-clock is used.
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Table 1.21.15 Electrical characteristics (7478 group)
(VCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = -20 C to +85 C(Note), unless otherwise noted)
Symbol VOH Parameter "H" output voltage P00 to P07, P10 to P17 P40 to P43 "L" output voltage P00 to P07, P10 to P17 P40 to P43 Hysteresis P00 to P07 P30 to P33 Hysteresis RESET Hysteresis P14/RxD P16/SCLK "L" input current P00 to P07, P10 to P17 P30 to P32, P40 to P43 P50 to P53 "L" input current P33 "L" input current P20 to P27 "L" input current XIN, RESET "H" input current P00 to P07, P10 to P17 P30 to P32, P40 to P43 P50 to P53 "H" input current P33 "H" input current P20 to P27 "H" input current XIN, RESET Test conditions VCC = 5 V, IOH = -5 mA VCC = 3 V, IOH = -1.5 mA VCC = 5 V, IOL = 10 mA VCC = 3 V, IOL = 3 mA VCC VCC VCC VCC = = = = 5 3 5 3 V V V V VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC = = = = = = = = = = = = 5 3 5 3 5 3 5 3 5 3 5 3 V V V V V V V V V V V V 0.5 0.3 0.5 0.3 0.5 0.3 -5 -3 -1.0 -0.35 -5 -3 -5 -3 -5 -3 5 3 5 3 5 3 5 3 14 7 3.6 15 8 4 80 40 4 2 1 12 8 1 10 5.5 Min. 3.0 2.0 2.0 1.0 Limits Typ. Max. Unit V V V V V V V V V V A A mA mA A A A A A A
A A A A A A A A mA mA mA mA mA mA A A
VOL VT+ - VT- VT+ - VT- VT+ - VT-
When used as RxD or SCLK VI = 0 V Not use pull-up transistor VI = 0 V Use pull-up transistor VI = 0V VI = 0 V Not use as analog input VI = 0 V XIN is at stop mode VI = VCC, Not use pull-up transistor VI = VCC VI = VCC Not use as analog input VI = VCC XIN is at stop mode At system op- f(XIN) = 8 MHz eration,
A-D conversion is not executed At system operation, A-D conversion is executed
IIL
-0.25 -0.08
-0.5 -0.18
IIL IIL IIL
VCC = 5 V VCC = 3 V VCC VCC VCC VCC VCC VCC = = = = = = 5 3 5 3 5 3 V V V V V V 7 3.5 1.8 7.5 4 2 30 15 2 1 0.5 3 2 0.1 1 2.0
IIH
IIH IIH IIH
VCC = 5 V VCC = 3 V VCC = 5 V V V V V V V V
f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz
ICC
Power source current
VCC = 3 At low-speed mode, Ta = 25C, low- VCC = 5 power mode, f (XCIN) = 32 kHz, A-D VCC = 3 conversion is not executed f(XIN) = 8 MHz VCC = 5 At wait mode f(XIN) = 4 MHz VCC = 3 At wait mode, Ta = 25C, low- VCC = 5 power mode, f (XCIN) = 32 VCC = 3 kHz At stop mode, VCC = 5 V
mA mA mA
A A A A V
Ta = 25 C Ta = 85 C
VRAM
RAM retention voltage
Stop all oscillation
Note: -40 C to +85 C for extended operating temperature version.
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Table 1.21.16 A-D converter characteristics (7478 group)
(VCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = -20 C to +85 C(Note 1), unless otherwise noted)
Symbol -- -- TCONV VREF RLADDER VIA Parameter Resolution Absolute accuracy Conversion time Reference input voltage Ladder resistance value Analog input voltage VCC = 4.5 V to 5.5 V, f(XIN) = 8 MHz VCC = 2.7 V to 5.5 V, f(XIN) = 4 MHz 0.5VCC (Note 2) 2 0 Test conditions Min. Limits Typ. Max. 8 3 12.5 25 VCC 5 10 VREF Unit bits LSB s s V k V
Notes 1: -40 C to +85 C for extended operating temperature version. 2: Set the VREF voltage to 0.5 V or more and 2 V or more. When using no A-D converter, connect it to VCC.
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1.21.2 Timing requirements, switching characteristics (1) 7470/7471 group timing requirements, switching characteristics Table 1.21.17 shows the timing requirements and switching characteristics of the 7470/7471 group. Figure 1.21.1 shows the timing chart. Table 1.21.17 Timing requirements and switching characteristics (7470/7471 group) (VCC = 4.0 V to 5.5 V, VSS = 0V, Ta = -20 C to +85C, f(XIN) = 4 MHz)
Symbol tc(CLK) tWH(CLK) tWL(CLK) tsu(SIN-CLK) th(CLK-SIN) td(CLK-SOUT) Serial Serial Serial Serial Serial Serial I/O I/O I/O I/O I/O I/O Parameter clock input cycle time clock input "H" pulse width clock input "L" pulse width input set up time input hold time output delay time Min. 1000 400 400 200 200 Limits Typ. Max. Unit ns ns ns ns ns ns
150
tc(CLK) tWL(CLK)
0.8VCC 0.8VCC 0.2VCC 0.2VCC
tWH(CLK)
0.8VCC
CLK
tsu(SIN-CLK)
0.8VCC
th(CLK-SIN)
0.8VCC 0.2VCC
SIN
td(CLK-SOUT)
0.2VCC
SOUT
Fig. 1.21.1 Timing chart (7470/7471 group)
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(2) 7477/7478 group timing requirements, switching characteristics Table 1.21.18 shows the timing requirements and switching characteristics of the 7477/7478 group. Figure 1.21.2 shows the timing chart. Table 1.21.18 Timing requirements and switching characteristics (7477/7478 group) (VCC = 4.5 V to 5.5 V, VSS = 0V, Ta = -20 C to +85C(Note), f(XIN) = 8 MHz)
Symbol tc(SCLK) tWH(SCLK) tWL(SCLK) tsu(RXD-SCLK) th(SCLK-RXD) td(SCLK-TXD) tc(SCLK) tWH(SCLK) tWL(SCLK) Serial Serial Serial Serial Serial Serial Serial Serial Serial I/O I/O I/O I/O I/O I/O I/O I/O I/O Clock synchronous Parameter clock input cycle time clock input "H" pulse width clock input "L" pulse width input set up time input hold time output delay time clock input cycle time clock input "H" pulse width clock input "L" pulse width Min. 2000 880 880 160 80 500 220 220 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns
100
Note: -40 C to +85 C for extended operating temperature version.
Clock asynchronous
tc(SCLK) tWL(SCLK)
0.8VCC 0.8VCC 0.2VCC 0.2VCC
tWH(SCLK)
0.8VCC
SCLK
tsu(RXD-SCLK)
0.8VCC
th(SCLK-RXD)
0.8VCC 0.2VCC
RXD
td(SCLK-TXD)
0.2VCC
TXD
Fig. 1.21.2 Timing chart (7477/7478 group)
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1.21.3 Power source current standard characteristics The power source current standard characteristics described in this section are mentioned as an characteristic example of the 7470/7471/7477/7478 group but not guaranteed by us. For standard values, refer to "1.21.1 Electrical characteristics." Figure 1.21.3 shows the power source current standard characteristics measuring circuit.
1
In ordinary mode (f(XIN ) = 8 MHz, 4 MHz)
M3747x
ICC VCC
2 In low-speed mode (f(XCIN ) = 32 kHz, 7471/7478 group) M3747x
ICC VCC
VSS
VSS
A
0 V to 5.5 V
XIN
XOUT 0 V to 5.5 V
A
XCIN XCOUT
Fig. 1.21.3 Power source current standard characteristics measuring circuit
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(1) 7470/7471 group power source current standard characteristics Figure 1.21.4 to Figure 1.21.6 show the ICC - VCC characteristics of the 7470/7471 group.
[Measuring condition : 25 C, f(X IN) = 8 MHz]
9.0
8.0 In ordinary mode
Power source current I CC [mA]
7.0
6.0
5.0
4.0
3.0
2.0 In wait mode 1.0 In stop mode 0.0 2.0 3.0 4.0 5.0 6.0 7.0
Power source voltage V CC [V]
Fig. 1.21.4 ICC - VCC characteristics (f(XIN) = 8 MHz, 7470/7471 group)
[Measuring condition : 25 C, f(XIN) = 4 MHz]
Power source current I CC [mA]
5.0 In ordinary mode 4.0
3.0
2.0 In wait mode 1.0 In stop mode 0.0 2.0 3.0 4.0 5.0 6.0 7.0
Power source voltage VCC [V]
Fig. 1.21.5 ICC - VCC characteristics (f(XIN) = 4 MHz, 7470/7471 group)
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[Measuring condition : 25 C, f(XCIN) = 32 kHz]
40.0
Power source current I CC [A]
In low-speed mode 30.0
20.0
10.0
In wait mode In stop mode 0.0 2.0 3.0 4.0 5.0 6.0 7.0
Power source voltage VCC [V]
Fig. 1.21.6 ICC - VCC characteristics (f(XCIN) = 32 kHz, 7471 group)
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(2) 7477/7478 group power source current standard characteristics Figure 1.21.7 to Figure 1.21.9 show the ICC - VCC characteristics of the 7477/7478 group.
[Measuring condition : 25 C, f(X IN) = 8 MHz]
8.0 In ordinary mode 7.0
Power source current I CC [mA]
6.0
5.0
4.0
3.0
2.0 In wait mode 1.0 In stop mode 0.0 2.0 3.0 4.0 5.0 6.0 7.0
Power source voltage VCC [V]
Fig. 1.21.7 ICC - VCC characteristics (f(XIN) = 8 MHz, 7477/7478 group)
[Measuring condition : 25 C, f(X IN) = 4 kHz]
5.0
Power source current I CC [mA]
In ordinary mode 4.0
3.0
2.0 In wait mode 1.0 In stop mode 0.0 2.0 3.0 4.0 5.0 6.0 7.0
Power source voltage VCC [V]
Fig. 1.21.8 ICC - VCC characteristics (f(XIN) = 4 MHz, 7477/7478 group)
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[Measuring condition : 25 C, f(XCIN ) = 32 kHz]
30.0
Power source current I CC [A]
In low-speed mode
20.0
10.0
In wait mode In stop mode 0.0 2.0 3.0 4.0 5.0 6.0 7.0
Power source voltage VCC [V]
Fig. 1.21.9 ICC - VCC characteristics (f(XCIN) = 32 kHz, 7478 group)
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1.21.4 Port standard characteristic The port standard characteristics described in this section are mentioned as a characteristic example of the 7470/7471/7477/7478 group but not guaranteed by us. For standard values, refer to "1.21.1 Electrical characteristics." Figure 1.21.10 shows the port standard characteristic measuring circuits.
1 IOH-VOH characteristic
2 IOL-VOL characteristic
3 IIL-VIL characteristic
measuring circuit
M3747x
0 V to 5.5 V VCC
measuring circuit
M3747x
VCC
measuring circuit
M3747x
0 V to 5.5 V VCC
A
P00 IOH
IOL P00 IIL
A
P00
A
VSS 0 V to 5.5 V VSS
VSS
Fig. 1.21.10 Port standard characteristic measuring circuits
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(1) 7470/7471 group port standard characteristic Figure 1.21.11 to Figure 1.21.13 show the port standard characteristics of the 7470/7471 group.
[Measuring condition : Port P0 0, 25 C] -60.0 -50.0
"H" output current I OH [mA]
-40.0 VCC = 5 V -30.0 -20.0 -10.0 0.0 -5.0 VCC = 3 V
-4.0
-3.0
-2.0
-1.0
0.0
"H" output voltage VOH -VCC [V]
Fig. 1.21.11 IOH - VOH characteristics of programmable I/O port (CMOS output) P-channel side (7470/7471 group)
[Measuring condition : Port P0 0, 25 C] 60.0 VCC = 5 V 50.0
"L" output current IOL [mA]
40.0 30.0 20.0 10.0 VCC = 3 V
0.0
1.0
2.0
3.0
4.0
5.0
"L" output voltage VOL [V]
Fig. 1.21.12 IOL - VOL characteristics of programmable I/O port (CMOS output) N-channel side (7470/7471 group)
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[Measuring condition : Port P0 0, 25 C] -0.7
VCC = 5 V
Supply current I IL [mA] 0.07/div
VCC = 3 V 0.0 -5.0
-4.0
-3.0
-2.0
-1.0
0.0
Supply voltage VIL -VCC [V]
Fig. 1.21.13 IIL - VIL characteristics of programmable I/O port (CMOS output) pull-up transistor (7470/7471 group)
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(2) 7477/7478 group port standard characteristic Figure 1.21.14 to Figure 1.21.16 show the port standard characteristics of the 7477/7478 group.
[Measuring condition : Port P0 0, 25 C] -60.0 -50.0
"H" output current I OH [mA]
VCC = 5 V
-40.0 -30.0 -20.0 VCC = 3 V -10.0 0.0 -5.0
-4.0
-3.0
-2.0
-1.0
0.0
"H" output voltage VOH -VCC [V]
Fig. 1.21.14 IOH - VOH characteristics of programmable I/O port (CMOS output) P-channel side (7477/7478 group)
[Measuring condition : Port P0 0, 25 C] 60.0 VCC = 5 V 50.0
"L" output current IOL [mA]
40.0 30.0 20.0 10.0 VCC = 3 V
0.0
1.0
2.0
3.0
4.0
5.0
"L" output voltage VOL [V]
Fig. 1.21.15 IOL - VOL characteristics of programmable I/O port (CMOS) N-channel side (7477/7478 group)
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[Measuring condition : Port P0 0, 25 C] -0.6 VCC = 5 V
Supply current I IL [mA] 0.12/div
VCC = 3 V
0.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 Supply voltage VIL -VCC [V]
Fig. 1.21.16 IIL - VIL characteristics of programmable I/O port (CMOS output) pull-up transistor (7477/7478 group)
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1.21.5 A-D conversion standard characteristic (1) Relative precision (7470/7471 group) Figure 1.21.17 to Figure 1.21.18 show the A-D conversion standard characteristics on the relative precision of the 7470/7471 group. In the graph, the lower line indicates a deviation from the ideal value at the point where the output code changes, namely, relative precision error (ERROR). For example, in Figure 1.21.17, the change of "3F16 to 4016" of the output code occurs ideally at the point of IN0 = 757.32 mV. However, since the relative precision error is -3.567 mV, "757.32 - 3.567 = 753.753 mV" represents a measuring change point. In the graph, the upper line indicates an input voltage width (1 LSB WIDTH) in which the output code is the same. For example, in Figure 1.21.17, since the measured value of input voltage width, when the output code is "3F16", is 10.701 mV, the differential nonlinear error on the relative precision represents "10.701 -11.89 = -1.189 mV (-0.1 LSB)".
Fig. 1.21.17 A-D conversion standard characteristics, relative precision error (1)
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Fig. 1.21.18 A-D conversion standard characteristics, relative precision error (2)
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(2) Absolute precision Figure 1.21.19 to Figure 1.21.23 show the A-D conversion standard characteristics on the absolute precision of the 7470/7471/7477/7478 group. In the graph, the lower line indicates a deviation from the ideal value at the point where the output code changes, namely, absolute precision error (ERROR). For example, in Figure 1.21.17, the change of "3F16 to 4016" of the output code occurs ideally at the point of IN0 = 762 mV. However, since the absolute precision error is -8.4 mV, "762 - 8.4 = 753.6 mV" represents the measuring change point. In the graph, the upper line indicates an input voltage with (1 LSB WIDTH) in which the output code is the same. For example, since the measured value of input voltage width, when the output code is "3F16", is 10.8 mV, the differential nonlinear error represents "10.8 - 12 = -1.2 mV (-0.1 LSB)".
Fig. 1.21.19 A-D conversion standard characteristics, absolute precision error (1)
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Fig. 1.21.20 A-D conversion standared characteristics, absolute precision error (2)
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Fig. 1.21.21 A-D conversion standard characteristics, absolute precision error (3)
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Fig. 1.21.22 A-D conversion standard characteristics, absolute precision error (4)
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Fig. 1.21.23 A-D conversion standard characteristics, absolute precision error (5)
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CHAPTER 2 APPLICATION
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 I/O pins Interrupts Timers Serial I/O A-D converter Reset Oscillation circuit Low-power dissipation function Countermeasures against noise Notes on programming Differences between 7470/7471 group and 7477/7478 group Example of application circuit
2.12
APPLICATION
2.1 I/O pins
2.1 I/O pins
2.1.1 I/O port
7470
7471
7477
7478
(1) Port register Table 2.1.1 shows a memory allocation of port register corresponding to each port. Table 2.1.1 Port register memory allocation Address of port register Port 7470 group 7471 group 7477 group 7478 group P0 00C016 00C016 00C016 00C016 P1 00C216 00C216 00C216 00C216 P2 00C416 00C416 00C416 00C416 P3 00C616 00C616 00C616 00C616 P4 00C816 00C816 00C816 00C816 P5 - 00CA16 - 00CA16 Note: In the 7470/7477 group, P2 is 4 bits of b0 - b3 and P4 is 2 bits of b0 and b1. In the 7471/7478 group, P5 is 4 bits of b0 b3.
In Chapter 2, each page describes the corresponding products by using the following table.
M37470Mx/Ex-XXXSP M37471Mx/Ex-XXXSP/FP M37477Mx/E8-XXXSP/FP, M37477Mx/E8TXXXSP/FP M37478Mx/E8-XXXSP/FP, M37478Mx/E8TXXXSP/FP
7470
7471
7477
7478
!
!
Non-corresponding products Corresponding products
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2.1 I/O pins
(2) Port Pi direction register (i = 0 to 5) 7470 7471 7477 7478
Switching between input and output for programmable I/O ports is performed by the port direction register corresponding to each port. Table 2.1.2 shows a memory allocation of the port direction register corresponding to each port and Figure 2.1.1 shows an example of port direction register setting. Table 2.1.2 Port direction register memory allocation Address of port direction register Port 7470 group 7471 group 7477 group 7478 group P0 00C116 00C116 00C116 00C116 P1 00C316 00C316 00C316 00C316 P2 00C516 00C516 - - P3 - - - - P4 00C916 00C916 00C916 00C916 P5 - - - - Note: In the 7470 group, P2 is 4 bits of b0 - b3 and P4 is 2 bits of b0 and b1. In the 7477 group, P4 is 2 bits of b0 and b1.
b7 When "6A16" (
b0
0 1 1 0 1 0 1 0 ) is set in the Port P0 direction register
Port P0 I/O direction
P07 P06 P05 P04 P03 P02 P01 P00
Input Output Output Input Output Input Output Input
Fig. 2.1.1 Example of port direction register setting
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(3) Pull-up control register 7470 7471 7477 7478
The ports shown in Table 2.1.3 can be pulled up by software. A pull-up operation can be performed by the P0 pull-up control register (address 00D016) and P1-P5 pull-up control register (address 00D116). Table 2.1.3 I/O ports that permit pull-up by software Register Port P0 pull-up control register Port P1-P5 pull-up control register* Device Control by 1-bit unit Control by 4-bit unit 7470 group P0 P1, P2, P4 7471 group P0 P1, P2, P4, P5 7477 group P0 P1, P4 7478 group P0 P1, P4, P5 * : In the 7470/7477 group, the P1-P4 pull-up control register is arranged. Note: In the 7470 group, P2 is 4 bits of b0 - b3 and P4 is 2 bits of b0 and b4. In the 7477 group, P4 is 2 bits of b0 and b1. In the 7471/7478 group, P5 is 4 bits of b0 - b3.
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2.1.2 Notes on use 7470 7471 7477 7478
When using I/O pins, take the following points into consideration.
(1) Double function ports Table 2.1.4 shows double function ports. For setting, refer to a structure of each register. Table 2.1.4 Double function port and control register Control register Double function port Pin 7470/7471 group 7477/7478 group 7477/7478 group 7470/7471 group Timer 12 mode register (T12M: Address 00F816) T0 P12 T1 Timer 34 mode register (T34M: Address 00F916) P13 Serial I/O control register Serial I/O mode register SIN RXD P14 (SIOSTS: Address 00E216) (SM: Address 00DC16) SOUT TXD Serial I/O mode register Serial I/O control register P15 CLK SCLK Serial I/O mode register Serial I/O control register P16 Serial I/O mode register Serial I/O control register P17 SRDY A-D control register (ADCON: Address 00D916) IN0 P20 IN1 A-D control register P21 IN2 A-D control register P22 IN3 A-D control register P23 IN4 A-D control register P24 IN5 A-D control register P25 IN6 A-D control register P26 IN7 A-D control register P27 INT0 Edge polarity selection register (EG: Address 00D416) P30 INT1 Edge polarity selection register P31 CNTR0 Edge polarity selection register, Timer 12 mode register P32 CNTR1 Edge polarity selection register, Timer 34 mode register P33 XCIN CPU mode register (CPUM: Address 00FB16) P50 XCOUT CPU mode register P51 Note: In the 7470/7477 group, P2 is 4 bits of b0 to b3. The 7470/7477 group is not provided with P5.
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APPLICATION
2.1 I/O pins
(2)Description of Pull-up control 7470 7471 7477 7478
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When pulling up a port by software, take the following points into consideration. q When P1 is used in the serial I/O mode, the pull-up settings corresponding to P14 to P17 are invalidated. (Pull-up is impossible.) q Pull-up control is exerted in the following bit units. P0 : 1-bit unit P1 to P5 : 4-bit unit When using an external pull-up resistor and software pull-up control for the same port in combined form, use P0, which can be controlled in bit units. (3)Notes on external circuit design for I/O ports 1 When designing an external circuit for I/O ports, be sure to set the following items within the standard value range. q Sum output current q Peak output current q Average output current Figure 2.1.2 shows the example of external circuit design for I/O port.
M3747x
VCC=5 V "L" sum output current Maximum standard value < 60 mA IOL0+IOL1+IOL2=36 mA
R0=250 V
P00
IOL0=12 mA
P01
IOL1=12 mA
"L" peak output current IOL0=IOL1=IOL2=12 mA
< 20 mA
R1=250 R2=250
V
"L" average output current (within 100 ms)
V
P02
IOL2=12 mA
12 mA!10 ms!5 = 6 mA < 10 mA 100 ms
Ports P00 - P02 Timing of LED on (duty ratio: 50 %) 10 ms 10 ms
V: LED (VF= 2 V) used
Fig. 2.1.2 Example of external circuit design for I/O port
2 When performing multiple key-in operations by forming a key matrix, design in consideration of the port input current for multiple key-in operations.
For other notes, refer to "1.10 I/O Pins."
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2.2 Interrupts
2.2 Interrupts
7470
7471
7477
7478
2.2.1 Memory allocation Figure 2.2.1 shows a memory map of interrupt related registers.
Address
00D416
Edge polarity selection register (EG)
00FC16 00FD16 00FE16 00FF16
Interrupt request register 1 (IR1) Interrupt request register 2 (IR2) Interrupt control register 1 (IE1) Interrupt control register 2 (IE2)
Fig. 2.2.1 Memory map of interrupt related registers
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APPLICATION
2.2 Interrupts
2.2.2. Processor status register (PS) 7470 7471 7477 7478
The Processor status register consists of 8 bits. Figure 2.2.2 shows the structure of the Processor status register. Bit 2 related to interrupts is described below. 2 Interrupt disable flag: b2 The interrupt disable flag controls the acceptance of interrupt requests other than the BRK instruction. When this flag is "1," the acceptance of interrupt requests is disabled. When the flag is "0," the acceptance of interrupt requests is enabled. The instruction to set this flag to "1" is the SEI instruction and the instruction to set this flag to "0" is the CLI instruction. At a branch to an interrupt processing routine, this flag is automatically set to "1," thereby multiple interrupts are disabled. To use multiple interrupt, set this flag to "0" by using the CLI instruction in the interrupt processing routine.
Processor status register
b7 b2 1
Undefined
b0 Undefined
Processor status register (PS)
b 0 1 2 3 4 5 6 7
b7 b0
Flag name C : Carry flag Z : Zero flag I : Interrupt disable flag D : Decimal mode flag B : Break flag T : Index X mode flag V : Overflow flag N : Negative flag
The value in
denotes the initial value immediately after reset release.
Fig. 2.2.2 Structure of Processor status register
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2.2 Interrupts
2.2.3 Application example 7470 7471 7477 7478
(1)External event detection by CNTR To detect a rising edge or a falling edge of the level of an input pin by using a pin other than the INT0 pin and the INT1 pin, it is possible to use the CNTR pin. Examples of use are shown below. q When the CNTR0 pin is used CNTR interrupt +1 1 Set the edge polarity selection register. * Select a CNTR0 edge polarity. * Select CNTR0 as an interrupt source. 2 Clear the CNTR interrupt request bit to "0." 3 Execute the NOP instruction. 4 Set the CNTR interrupt enable bit to "1." q When the CNTR1 pin is used Timer 3 interrupt +1,+2 1 Stop the count operation of timer 3. 2 Select CNTR1 as a count source of timer 3. 3 Select a CNTR1 edge polarity by the Edge polarity selection register. 4 Set timer 3 to "0." 5 Clear the timer 3 interrupt request bit to "0." 6 Set the timer 3 interrupt enable bit to "1." 7 Start the count operation of timer 3. +1: It is possible to use the CNTR0 pin for a timer interrupt and the CNTR1 pin for a CNTR interrupt. +2: It is possible to use timer 4 as an interrupt source.
2.2.4 Notes on use For notes on use, refer to "1.11 Interrupts."
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APPLICATION
2.3 Timers
2.3 Timers
2.3.1 Memory allocation Figure 2.3.1 shows a memory map of timer related registers.
7470
7471
7477
7478
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Address
00D416 00D516 00D616
Edge polarity selection register (EG) Input latch register (ILR)
00F016 00F116 00F216 00F316
Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4)
00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16
Timer FF register (TF) Timer 12 mode register (T12M) Timer 34 mode register (T34M) Timer mode register 2 (TM2) CPU mode register (CPUM) Interrupt request register 1 (IR1) Interrupt request register 2 (IR2) Interrupt control register 1 (IE1) Interrupt control register 2 (IE2)
Fig. 2.3.1 Memory map of timer related registers
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2.3 Timers
2.3.2 Application example 7470 7471 7477 7478
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(1) Each mode of timer For timers 1, 2, 3 and 4, the following 5 operation modes are available. For each timer mode and the details of it, refer to "1.12 Timers." 1 2 3 4 5 Timer mode Event counter mode Pulse output mode External pulse width measurement mode PWM mode
Each timer mode has relation to the T0, T1, CNTR0 and CNTR1 pins as shown in Table 2.3.1. There are some modes that cannot be used for some combinations of timer and pin. Consider this when designing timers. Table 2.3.1 Relation between timer-used pins and modes Pin T0 T1 CNTR0 Timer Pulse output x Event counter mode Timer 1 mode Timer 2 Timer 3 x x Pulse output mode x PWM mode x x
CNTR1 x x Event counter mode
Timer 4
x
Event counter mode External pulse width measurement mode External pulse width measurement mode
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APPLICATION
2.3 Timers
(2) Example of use of each mode 7470 7471 7477 7478
x
An example of use of each mode is shown below. 1 Timer mode: One-second measurement (timer function)
,
x
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Outline: Divide the clock by the timer. Count one second by a timer 1 interrupt that is generated at an internal of 0.4 ms. Cause the timer to count up at each second. Specifications: Divide f(XCIN) = 32 kHz by timer 1 to generate an interrupt. Check the value of the counter that counts with an timer 1 interrupt by the main routine. If one second has elapsed, execute timer count-up processing. Figure 2.3.2 shows an example of control procedure.
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2.3 Timers
7470 7471 7477 7478
x
,
x
,
RESET Initialization
Set the interrupt disable flag (each interrupt disabled)
Clear the timer 1 interrupt enable bit (timer 1 interrupt disabled) Set the timer 12 mode register
! ! ! ! ! 1 0 1 T12M (Address 00F816) Timer 1 count stop Timer 1 count source Internal clock Timer 1 internal clock count source f(XCIN)
Set the CPU mode register
! ! 1 1 ! ! 0 0 CPUM (Address 00FB 16) Fixed to "0" Select XCIN, XCOUT XCOUT drive capacity High power
Wait the f(XCIN) oscillation stabilizing time Set the Timer 1 to "7F 16" Set the Timer 12 mode register
! ! ! ! ! 1 0 0 T12M (Address 00F816) Timer 1 count start
q For concrete time, ask the oscillator manufacture for information. 7F16 q 1 second = 1/32 kHz ! (127+1) ! 250
Dividing ratio Count by interrupt processing
Clear the timer 1 interrupt request bit Set the timer 1 interrupt enable bit (Timer 1 interrupt enabled) Interrupt at every 0.4 ms Clear the interrupt disable flag (each interrupt enabled) 1 second counter + 1 Timer 1 interrupt
Clock stop ? N
1 second has elapsed ? (1 second counter = 250 ?)
Y
=
RTI
N
Y
Clear 1 second counter Clock count up (second-year)
V
Processing for timer set is completed ?
N
Y
Set the Timer 1 to "7F 16" q When re-starting the clock from zero second after completing to set the clock, set timers again.
Clear the Timer 1 interrupt request bit q Set the timer so that every processing within the loop marked V may be executed in a period of 1 second or less.
Clear 1 second counter
Fig. 2.3.2 Example of control procedure [Clock function]
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APPLICATION
2.3 Timers
2 Event counter mode: Frequency measurement 7470 7471 7477 7478
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Outline: The frequency of the pulse input to the CNTR0 pin ("H" active) is measured by the number of events in a certain period. Specifications: A count operation is started specifying the count source of timer 1 as CNTR0. Timer 2 (count source: f(XIN)/64) detects 1 ms and the frequency of the pulse input to CNTR0 is calculated from the number of events counted within 1 ms. Note: The number of events of an input pulse is specified as 255 or less within 1 ms. Figure 2.3.3 shows an example of measurement method of frequency and Figure 2.3.4 shows an example of control procedure.
Timer 2 interrupt request bit
Count start
1 ms has elapsed
Count stop
CNTR0
Count start
X times
Count stop
q Pulse frequency of CNTR 0 input = X times 1 ms kHz
Fig. 2.3.3 Example of measurement method of frequency
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2.3 Timers
7470 7471 7477 7478
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Frequency measurement routine
Clear the timer 2 interrupt enable bit (Timer 2 interrupt disabled)
Set the Timer 12 mode register
! ! ! 1 ! ! ! 1 T12M (Address 00F816) Timer 1 count stop Timer 2 count stop
Set the Edge polarity selection register
! ! ! ! ! 1 ! ! EG (Address 00D416) CNTR0 rising edge selected
Set the Timer 12 mode register
0 1 0 1 ! ! 1 1 T12M (Address 00F816) Timer 1 count source CNTR0 Timer 2 count source Internal clock Timer 2 internal clock count source f(XIN)/64
Set the Timer 1 to "FF 16" Set the Timer 2 to "7C 16" Clear the timer 2 interrupt request bit Set the timer 2 interrupt enable bit (Timer 2 interrupt enabled) Set the Timer 12 mode register
0 1 0 0 ! ! 1 0 T12M (Address 00F816) Timer 1 count start Timer 2 count start
V According to required accuracy, the event count value within 1 ms is detected repeatedly, and its results are averaged.
Timer 2 interrupt Set the Timer 12 mode register
0 1 0 1 ! ! 1 1 T12M (Address 00F816) Timer 1 count stop Timer 2 count stop
Read timer 1 (Timer 1 set value FF 16) - (Timer 1 read value) Event count value within 1 ms
RTS
RTI
Fig. 2.3.4 Example of control procedure [Frequency measurement]
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APPLICATION
2.3 Timers
3 Pulse output mode: Piezoelectric buzzer output 7470 7471 7477 7478
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Outline: The pulse output function of the timer is applied for a piezoelectric buzzer output. Specifications: A square wave obtained by dividing the clock f(XIN) = 8 MHz into about 2 kHz is output from the T0 pin. While the buzzer output stops, the level of the T0 pin is fixed at "H." Figure 2.3.5 shows an example of a peripheral circuit. Figure 2.3.6 shows a connection of the timer and setting of the division ratio. Figure 2.3.7 shows an example of control procedure.
While the piezoelectric buzzer output stops, the "H" level is output.
M3747x
T0
250 s 250 s
Set the division ratio so that the underflow period of timer 1 may be equal to this value.
Fig. 2.3.5 Example of a peripheral circuit [Pulse output mode]
Fix
Timer 1
f(XIN) 8MHz
1/16
1/125
1/2
T0
Fig. 2.3.6 Connection of timer and setting of division ratio
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2.3 Timers
7470 7471 7477 7478
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RESET
Initialization
Set the interrupt disable flag (each interrupt disabled)
Clear the timer 1 interrupt enable bit (Timer 1 interrupt disabled) Set the Timer 12 mode register
! ! ! ! 1 0 0 1 T12M (Address 00F816) Timer 1 count stop Timer 1 count source Internal clock Timer 1 internal clock count source f(XIN)/16 T0 output selected
T A piezoelectric buzzer output stops.
Set the Timer mode register 2
! ! ! ! ! ! ! 1 TM2 (Address 00FA16) Timer 1 division flip flop set enabled
Set the Timer FF register
! ! ! ! ! ! ! 0 TF (Address 00F716) Timer 1 division flip flop initial value 0
Set the port P12 as an output Port P12 "H" Set the Timer 1 to "7C 16" Set the Timer 1 interrupt enable bit (Timer 1 interrupt enabled) Clear the interrupt disable flag (each interrupt enabled)
T 2 kHz =
8 MHz 16 ! (124+1) ! 2
Timer 1 overflow divided by 2 7C16 Count by interrupt processing
=
Fixed dividion ratio
Main processing
T A piezoelectric buzzer request generated in the main processing is processed in the output unit.
Output unit A piezoeletric buzzer is requested ? N (= No request) T Buzzer output stop Y (= 0 Request) N Immediately after no request? Y T Buzzer output start
Set the Timer 12 mode register
! ! ! ! 1 0 0 1 T12M (Address 00F816) Timer 1 count stop
Set the Timer 1 to "7C 16" Set the Timer 12 mode register
! ! ! ! 1 0 0 0 T12M (Address 00F816) Timer 1 count start
Port P12 "H"
Fig. 2.3.7 Example of control procedure [Piezoelectric buzzer output]
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APPLICATION
2.3 Timers
4 Pulse width measurement mode: Feedback control of phase control signal 7470 7471 7477 7478
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Outline: The phase control signal is adjusted by using the pulse width measurement mode. Specifications: The M3747x controls a load by phase control. At this time, the width of the pulse output from the load as a feedback signal is measured. With this result, the control over the load is compensated. Figure 2.3.8 shows an example of peripheral circuit and Figure 2.3.9 shows an example of control procedure.
M3747x
CNTR0
Load
Port VAC
Fig. 2.3.8 Example of peripheral circuit [Pulse width measurement mode]
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2.3 Timers
7470 7471 7477 7478
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Pulse width measurement routine
Set the Timer 34 mode register
! ! ! ! 1 ! ! ! T34M (Address 00F916) Timer 4 count stop
Set the Edge polarity selection register
! ! ! 0 ! 0 ! ! EG (Address 00D416) Select the measurement of CNTR 0 "H" width Interrupt CNTR0 selected
Set the Timer 34 mode register
! 1 ! ! 1 ! ! ! T34M (Address 00F916) Timer 4 count source select according to an input pulse External pulse width measurement mode selected
Set the Timer 4 to "FF 16"
Clear the CNTR interrupt request bit
Set the Timer 34 mode register
! 1 ! ! 0 ! ! ! T34M (Address 00F916) Timer 4 count start
CNTR interrupt request ?
N
Y
T Measurement completed
Set the Timer 34 mode register
! 1 ! ! 1 ! ! ! T34M (Address 00F916) Timer 4 count stop
Read Timer 4
(Timer 4 set value FF 16) - (Timer 4 read value) Input pulse "H" width measurement value
RTS
Fig. 2.3.9 Example of control procedure [Pulse width measurement mode]
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APPLICATION
2.3 Timers
5 PWM mode: Analog output 7470 7471 7477 7478
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Outline: An analog output is performed by using the PWM function of the timer. Specifications: A count source of Timer 3 and Timer 4 is selected and a PWM waveform is output from the T1 pin. The PWM waveform is converted into an analog voltage by the external circuit of the T1 pin, and then this voltage is output. Note: The analog voltage to be output varies depending on the duty of the PWM waveform. Figure 2.3.10 shows an example of peripheral circuit and Figure 2.3.11 shows an example of control procedure.
M3747x
3:2 5V
T1
0
Fig. 2.3.10 Example of peripheral circuit [PWM mode]
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2.3 Timers
7470 7471 7477 7478
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Analog output routine
Set the Timer 34 mode register
! ! ! ! 1 ! ! 1 T34M (Address 00F916) Timer 3 count stop Timer 4 count stop
Set port P13 as an output
Set the Timer 34 mode register
1 ! ! ! 1 ! ! 1 T34M (Address 00F916) Select timer 3 count source Select timer 4 count source Select T1 output
Set the Timer 3
Set the Timer 4
Set the Timer mode register 2
1 ! ! ! ! ! ! ! TM2 (Address 00FA16) Select PWM mode
Set the Timer 34 mode register
1 ! ! ! 0 ! ! 0 T34M (Address 00F916) Timer 3 count start Timer 4 count start
RTS
Fig. 2.3.11 Example of control procedure [PWM mode]
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APPLICATION
2.3 Timers
2.3.3 Notes on use 7470 7471 7477 7478
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2 When using a 16-bit counter by using two timers, take the following points into consideration according to "1.12.5 Notes on use (2)." qThe timing at which the timer value and the read value change, when two 8-bit timers are connected in series, is shown in Figure 2.3.12, taking the case where timer 1 and timer 2 are connected as an example (When Timer 1 and Timer 2 are connected and the set value of the Timer 1 is 216 and the set value of the Timer 2 is 116). The count source of timer 2 is the overflow signal of timer 1. In this case, the read value of timer 2 changes at the fall of the count source. When Timer 1 and Timer 2 are read continuously as a 16-bit counter, the count source of timer 2 changes at the falling edge of the count source of timer 1, so the A section can not be distinguished from the B section. Likewise, the C section cannot be distinguished from the D section.
Timer 1 count source Timer 1 value Timer 1 read value Timer 1 interrupt request Timer 2 count source Timer 2 value
0 FF 0 FF 2 1 1 0 0 FF FF 1 1 0 0 FF FF 1 1 0 0 FF FF 1 1 0 0
Writing to timer 1
A
Timer 2 read value Timer 2 interrupt request
1 0
BC
FF
D
0
Writing to timer 2
Fig. 2.3.12 Timing at which timer value and read value change in the case where two timers are connected in series 2 For other notes on use, refer to "1.12 timers."
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2.4 Serial I/O
2.4 Serial I/O
7470
7471
7477
7478
x
2.4.1 7470/7471 group memory allocation Figure 2.4.1 shows a memory map of serial I/O related registers in the 7470/7471 group.
x
Address
00DC16 00DD16 00DE16
Serial I/O mode register (SM) Serial I/O register (SIO) Serial I/O counter Byte counter
)
00FC16 00FD16 00FE16 00FF16
Interrupt request register 1 (IR1) Interrupt control register 1 (IE1)
Fig. 2.4.1 Memory map of serial I/O related registers in 7470/7471 group
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APPLICATION
2.4 Serial I/O
2.4.2 Application example 7470 7471 7477 7478
x
(1) Clock synchronous serial I/O mode Outline: Clock synchronous communication is performed among the 7470/7471 group. Specifications: M3747x 1 ......Transmit side in half-duplex communication * Synchronous clock: f(XIN)/16 * Port P17 is used as an SRDY signal input pin. M3747x 2 ......Receive side in half-duplex communication * Synchronous clock: External clock * SRDY signal output
x
Figure 2.4.2 shows an example of connections and Figure 2.4.3 shows an example of control procedure.
Use Full-duplex communication No use Half-duplex communication
M3747x 1
P17 CLK SOUT SIN
M3747x 2
SRDY CLK SIN SOUT
Fig. 2.4.2 Example of connections [Clock synchronous serial I/O mode, 7470/7471 group]
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2.4 Serial I/O
7470 7471 7477 7478
x
x
M3747x 1
Clear the serial I/O interrupt enable bit (Serial I/O interrupt disabled) Set port P17 to input Set the Serial I/O mode register
00!01 101 SM (Address 00DC16) Internal clock f(XIN)/16 Synchronous clock Internal clock Select SOUT, CLK Select port P17 - Mode Ordinary mode CMOS output
M3747x 2
Clear the serial I/O interrupt enable bit (Serial I/O interrupt disabled) Set port P14 to input Set the Serial I/O mode register
0 0 0 1 1 0 ! ! SM (Address 00DC 16) - Synchronous clock External clock Select SOUT, CLK SRDY signal output Select SRDY signal Mode Ordinary mode CMOS output
Clear the serial I/O interrupt request bit Set the serial I/O interrupt enable bit (Serial I/O interrupt enabled)
Clear the serial I/O interrupt request bit Set the serial I/O interrupt enable bit (Serial I/O interrupt enabled)
Write the transmit data into the Serial I/O register (Write the dummy data in the half-duplex communication)
Port P17 = "L" ? Y
N
Write the transmit data into the Serial I/O register
Serial I/O interrupt Serial I/O interrupt
Fig. 2.4.3 Example of control procedure [Clock synchronous serial I/O mode, 7470/7471 group]
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APPLICATION
2.4 Serial I/O
(2)Byte specification mode 7470 7471 7477 7478
x
x
Outline: Among the 7470/7471 group, transfer is performed for two or more microcomputers by using the clock synchronous byte specification mode. Specifications: Transmit side M3747x 1 * Synchronous clock: f(XIN)/32 * Port P17 is used as an SRDY signal input pin. * Port P10 is used as an transmit preparation command signal output pin. Receive side M3747x 2 , M3747x 3 , M3747x 4 * Synchronous clock: External clock * SARDY signal output * Port P10 is used as an transmit preparation command signal output pin. Figure 2.4.4 shows an example of connections and Figure 2.4.5 and 2.4.6 show an example of control procedure.
Transmit side (M3747x 1 )
Serial I/O mode register
0 0 0 0 1 1 1 0
* Set port P17 as an input * Connect a pull-up transistor to port P1 7 * Set port P10 as an output (Port P10: Transmit preparation command signal)
P17
CLK
SOUT
P10
SARDY CLK Serial data Transmit/receive preparation command signal
SRDY(SARDY) CLK
SIN
P10
SRDY(SARDY) CLK
SIN
P10
SRDY(SARDY) CLK
SIN
P10
* Set port P10 as an input (Port P10: Transmit/receive preparation command signal) * Set port P14 as an input
* Set port P10 as an input (Port P10: Transmit/receive preparation command signal) * Set port P14 as an input
* Set port P10 as an input (Port P10: Transmit/receive preparation command signal) * Set port P14 as an input
Serial I/O mode register
1 1 1 1 1 0 0 0 1
Serial I/O mode register
1 1 1 1 0 0 0 1
Serial I/O mode register
1 1 1 1 0 0 0
Byte counter (Initial value) = 0
Byte counter (Initial value) = 1
Byte counter (Initial value) = 2
Receive side 1 (M3747x 2 )
Receive side 2 (M3747x 3 )
Receive side 3 (M3747x 4 )
Fig. 2.4.4 Example of connections [Byte specification mode, 7470/7471 group]
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2.4 Serial I/O
7470 7471 7477 7478
x
x
Transmit side (M3747x 1 )
Clear the serial I/O interrupt enable bit (Serial I/O interrupt disabled) Set port P17 as an input Connect a pull-up transistor to port P17 Set port P10 as an output Set the serial I/O mode register
00001110 SM (Address 00DC16) Internal clock f(XIN)/32 Synchronous clock Internal clock Select SOUT, CLK Select port P17 - Mode Ordinary mode CMOS output
Receive side 1 (M3747x 2 )
Clear the serial I/O interrupt enable bit (Serial I/O interrupt disabled) Set port P14 as an input Set port P10 as an input Set the Serial I/O mode register
11111000 SM (Address 00DC 16) - Synchronous clock External clock Select SOUT, CLK Select SRDY signal output pin. Select SARDY signal Mode Byte specify mode N-channel open-drain output
Clear the serial I/O interrupt request bit Set the serial I/O interrupt enable bit (Serial I/O interrupt enabled)
Clear the serial I/O interrupt request bit Set the serial I/O interrupt enable bit (Serial I/O interrupt enabled) Transmit preparation signal port P10 "L"
Transmit preparation signal port P1 0 "L" ? Y
N
Port P17 = "H" ?
N
Set the initial value of "0" of the receive side 1 in the byte counter EoECEgEJEEEiE^C...eUeMeCPCAeaailCOC EZEbEg Write the dummy data into the Serial I/O register
Y Transmit preparation signal port P10 "H" Write the transmit data to receive side 1 into the Serial I/O register
Serial I/O interrupt
Write the transmit data to receive side 2 into the Serial I/O register
Serial I/O interrupt
Serial I/O interrupt
Write the transmit data to receive side 3 into the Serial I/O register
Serial I/O interrupt
Fig. 2.4.5 Example of control procedure (1) [Byte specification mode, 7470/7471 group]
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APPLICATION
2.4 Serial I/O
7470 7471 7477 7478
x
x
Receive side 2 (M3747x 3 )
Clear the serial I/O interrupt enable bit (Serial I/O interrupt disabled) Set port P14 as an input Set port P10 as an input Set the Serial I/O mode register
11111000 SM (Address 00DC16) - Synchronous clock External clock Select SOUT, CLK Select SRDY signal output pin. Select SARDY signal Mode Byte specify mode N-channel open-drain output
Receive side 3 (M3747x 4 )
Clear the serial I/O interrupt enable bit (Serial I/O interrupt disabled) Set port P14 as an input Set port P10 as an input Set the Serial I/O mode register
11111000 SM (Address 00DC16) - Synchronous clock External clock Select SOUT, CLK Select SRDY signal output pin Select SARDY signal Mode Byte specify mode N-channel open-drain output
Clear the serial I/O interrupt request bit Set the serial I/O interrupt enable bit (Serial I/O interrupt enabled)
Clear the serial I/O interrupt request bit Set the serial I/O interrupt enable bit (Serial I/O interrupt enabled)
Transmit preparation signal port P10 "L" ? Y
N
Transmit preparation signal port P10 "L" ? Y
N
Set the initial value of "1" of the receive side 2 in the Byte counter EoECEgEJEEEiE^C...eUeMeCPCAeaailCOC EZEbEg Write the dummy data into the Serial I/O register
Set the initial value of "2" of the receive side 3 in the Byte counter Write the dummy data into the Serial I/O register
Serial I/O interrupt
Serial I/O interrupt
Fig. 2.4.6 Example of control procedure (2) [Byte specification mode, 7470/7471 group]
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2.4 Serial I/O
2.4.3 7477/7478 group memory allocation 7470 7471 7477 7478
x
x
Figure 2.4.7 shows a memory map of serial I/O related registers in the 7477/7478 group.
Address
00E016 00E116 00E216 00E316 00E416
Transmit/receive buffer register (TB/RB) Serial I/O status register (SIOSTS) Serial I/O control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG)
00FC16 Interrupt request register 1 (IR1) 00FD16 00FE16 Interrupt control register 1 (IE1) 00FF16
Fig. 2.4.7 Memory map of serial I/O related registers in 7477/7478 group
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APPLICATION
2.4 Serial I/O
2.4.4 Application examples 7470 7471 7477 7478
x
(1) Clock synchronous serial I/O mode
x
Outline: Clock synchronous communication is performed among the 7477/7478 group. Specifications: M3747x 1 ......Transmit side in half-duplex communication. * Synchronous clock: BRG output (f(XIN)/4 or f(XIN)/16)/4. * Port P17 is used as an SRDY signal input pin. M3747x 2 ......Receive side in half-duplex communication * Synchronous clock: External clock * SRDY signal output Figure 2.4.8 shows an example of connections and Figure 2.4.9 shows an example of control procedure.
Use Full-duplex communication No use Half-duplex communication
M3747x 1
P17 SCLK TxD RxD
M3747x 2
SRDY SCLK RxD TxD
Fig. 2.4.8 Example of connections [Clock synchronous serial I/O mode, 7477/7478 group]
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2.4 Serial I/O
7470 7471 7477 7478
x
x
M3747x 1
Clear the serial I/O transmit interrupt enable bit (Serial I/O transmit interrupt disable) Clear the serial I/O receive interrupt enable bit (Serial I/O receive interrupt disable)
M3747x 2
Clear the serial I/O transmit interrupt enable bit (Serial I/O transmit interrupt disabled) Clear the serial I/O receive interrupt enable bit (Serial I/O receive interrupt disabled)
Set baud rate generator Set port P17 as an input Set the Serial I/O control register
1 1 1 1 ! 0 0 ! SIOCON (Address 00E2 16) Select BRG count source Synchronous clock BRG output divided by 4 SRDY output disabled Select transmit interrupt source Transmit enabled Receive enabled Clock synchronous serial I/O selected Serial I/O enabled NOP Clear the serial I/O transmit interrupt request bit Clear the serial I/O receive interrupt request bit
Set the Serial I/O control register
1 1 1 1 ! 1 1 ! SIOCON (Address 00E2 16) Select BRG count source Synchronous clock External clock SRDY output enabled Select transmit interrupt source Transmit enabled Receive enabled Clock synchronous serial I/O selected Serial I/O enabled
NOP Clear the serial I/O transmit interrupt request bit Clear the serial I/O receive interrupt request bit Set the serial I/O transmit interrupt enable bit (Serial I/O transmit interrupt enabled) Set the serial I/O receive interrupt enable bit (Serial I/O receive interrupt enabled) Write the transmit data into the Transmit buffer register (Write the dummy data in the half-duplex communication)
Set the serial I/O transmit interrupt enable bit (Serial I/O transmit interrupt enable) Set the serial I/O receive interrupt enable bit (Serial I/O receive interrupt enable)
N Port P17 = "L" ? Y Write the transmit data into the Transmit buffer register
Serial I/O transmit interrupt Serial I/O receive interrupt
Serial I/O transmit interrupt Serial I/O receive interrupt
Fig. 2.4.9 Example of control procedure [Clock synchronous serial I/O mode, 7477/7478 group]
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APPLICATION
2.4 Serial I/O
(2)Clock asynchronous serial I/O mode 7470 7471 7477 7478
x
x
Outline: Clock asynchronous communication is performed among the 7477/7478 groups. Specifications: M3747x 1 ......Transmit side in half-duplex communication f(XIN) * Baud rate: bps 4 x (XX16 + 1) x 16 M3747x 2 ...... Receive side in half-duplex communication f(XIN) * Baud rate: bps 4 x (XX16 + 1) x 16 "XX16" is a set value of the baud rate generator. Figure 2.4.10 shows an example of connections and Figure 2.4.11 shows an example of control procedure.
Use Full-duplex communication No use Half-duplex communication
M3747x 1
M3747x 2
TxD RxD
RxD TxD
Fig. 2.4.10 Example of connections [Clock asynchronous serial I/O mode, 7477/7478 group]
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2.4 Serial I/O
7470 7471 7477 7478
x
x
M3747x 1
Clear the serial I/O transmit interrupt enable bit (Serial I/O transmit interrupt disabled) Clear the serial I/O receive interrupt enable bit (Serial I/O receive interrupt disabled)
M3747x 2
Clear the serial I/O transmit interrupt enable bit (Serial I/O transmit interrupt disabled) Clear the serial I/O receive interrupt enable bit (Serial I/O receive interrupt disabled)
Set baud rate generator (Set "!!16" to BRG)
Set baud rate generator (Set "!!16" to BRG)
Set the Serial I/O control register
1 011!!00 SIOCON (Address 00E2 16) BRG count source f(XIN)/4 Synchronous clock BRG output divided by 16 - Select transmit interrupt source Transmit enabled Receive enabled Clock asynchronous serial I/O selected Serial I/O enabled
Set the Serial I/O control register
1 0 1 1!!0 0 SIOCON (Address 00E2 16) BRG count source f(XIN)/4 Synchronous clock BRG output divided by 16 - Select transmit interrupt source Transmit enabled Receive enabled Clock asynchronous serial I/O selected Serial I/O enabled
NOP Clear the serial I/O transmit interrupt request bit Clear the serial I/O receive interrupt request bit
NOP Clear the serial I/O transmit interrupt request bit Clear the serial I/O receive interrupt request bit
Set the serial I/O transmit interrupt enable bit (Serial I/O transmit interrupt enabled) Set the serial I/O receive interrupt enable bit (Serial I/O receive interrupt enabled) Write the transmit data into the Transmit buffer register
Set the serial I/O transmit interrupt enable bit (Serial I/O transmit interrupt enabled) Set the serial I/O receive interrupt enable bit (Serial I/O receive interrupt enabled) Write the transmit data to the Transmit buffer register in the full-duplex communication
Serial I/O transmit interrupt Serial I/O receive interrupt
Serial I/O transmit interrupt Serial I/O receive interrupt
Fig. 2.4.11 Example of control procedure [Clock asynchronous serial I/O mode, 7477/7478 group]
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APPLICATION
2.4 Serial I/O
2.4.5 Notes on use 7470 7471 7477 7478
For notes on use, refer to "1.13 Serial I/O."
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2.5 A-D converter
2.5 A-D converter
7470
7471
7477
7478
2.5.1 Memory allocation Figure 2.5.1 shows a memory map of A-D conversion related registers.
Address
00D916 00DA16
A-D control register (ADCON) A-D conversion register (AD)
00FC16 00FD16 00FE16 00FF16
Interrupt request register 1 (IR1)
Interrupt control register 1 (IE1)
Fig. 2.5.1 Memory map of A-D conversion related registers
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APPLICATION
2.5 A-D converter
2.5.2 Application examples 7470 7471 7477 7478
(1) A-D conversion value determination methods For improvement of the accuracy of A-D conversion results, we recommend you perform sampling several times to determine a value. The following A-D conversion value sampling methods are available (m, n: Arbitrary values based on the specification). Example: 1 Sampling 2 n times 2 Moving sampling 2 n times 3 Sampling (2 n + 2) times For value determination, the following methods are available. Example: [1] The sum of sampling result is divided by sampling times. [2] After execution of sampling (2 n + 2) times, the minimum value and the maximum value are excluded and then the remaining values are added and then divided by 2 n times. [3] When updating the average value calculated by [1]or [2], this average value is not updated if the difference from the previous value is m or more. In "2.5.2 Application examples, (2) Example of A-D conversion setting," an example of using the sampling methods 2 + 3 and the determination method [3] is shown.
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2.5 A-D converter
(2) Example of A-D conversion setting 7470 7471 7477 7478
An example of A-D conversion setting using the sampling methods 2 + 3 and the determination method [3] described on the previous page is shown below. Specifications: After execution of 6-time moving sampling the maximum value and the minimum value are excluded and then the remaining values are added. This result is divided by 4 (times). If the difference from the previous value is less than 5, the value is updated. If the same difference is 5 or more, it is not updated. Figure 2.5.2 shows an example of control procedure.
Minimum value
Maximum value
Sampling point A-D conversion result A616 A816 A916 A716 A816 AB16
A-D conversion routine Set the port P20 as an input Clear the A-D conversion interrupt request bit Set the A-D control register
0 ! ! 1 1 0 0 0 ADCON (Address 00D9 16) AD input pin P20/IN0 End conversion VREF is connected (Note 1) Fixed to "0"
T
N A-D conversion completed ? (Note 3) Y
The contents of A-D conversion register is read and stored into RAM. (ADRAM) AB16 After execution of 6-time samplings to this time, the minimum value and the maximum value are excluded and then the remaining values are added. A816+A916+A716+A816=2A016 Total of 4-time sampling 4 2A016 =A816 4
Wait the VREF stabilizing time (1.0 s or more) (Note 2) Set the A-D control register
0 ! ! 1 0 0 0 0 ADCON (Address 00D9 16) Clear the A-D conversion completion bit
5 or more
T
Notes 1: The 7477/7478 group is not provided with this bit. 2: Performs this operation only in the 7470/7471 group. 3: A termination of A-D conversion is verified by the state of the A-D conversion completion bit, the state of the A-D conversion completion interrupt request bit and a branch to the A-D conversion completion interrupt processing routine.
Compare with the previous fixed value
less than 5 Renewal of fixed value
RTS
Fig. 2.5.2 Example of A-D conversion control procedure
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2.5 A-D converter
2.5.3 Notes on use 7470 7471 7477 7478
The analog input internal equivalent circuit is shown in Figure 2.5.3. For correct A-D conversion, it is necessary that the internal capacitor should be completely charged within the specified time. The maximum value of output impedance of the analog input source required to terminate capacitor charging within this time is shown below. * At f(XIN) = 4 MHz, Approximately 10 k * At f(XIN) = 8 MHz, Approximately 2 k If the maximum value of output impedance exceeds the above value, take a proper measure, for example, insert a capacitor (0.1 F to 1 F) between analog input pin and VSS.
VCC C1=10 pF 50%
Port P2i/INi
(i=0 to 7)
R=4 k 60% SW1(Note 2) SW2
C2=6 pF 30%
VSS
VSS
(Note 1) Reference voltage generation circuit Switch tree Resistor ladder
Amplifier
VREF switch (Note 3)
VSS VREF
Notes 1: This is a parasitic diode of the output transistor. 2: SW1 is turned on only when the analog input pin is selected. 3: The VREF switch is not provided in the 7477/7478 group.
Fig. 2.5.3 Analog input internal equivalent circuit For other notes on use, refer to "1.14 A-D converter."
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2.6 Reset
2.6 Reset
2.6.1 Reset circuit Figure 2.6.1 shows an example of reset circuit.
7470
7471
7477
7478
M3747x
RESET
M3747x VCC
RESET
VCC
Supply voltage detection circuit
RESET, VCC pin number 32P
RESET
42P 25 22
56P 28 23
18 17
VCC
Fig. 2.6.1 Example of reset circuit
2.6.2 Notes on use For notes on use, refer to "1.15 Reset."
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APPLICATION
2.7 Oscillation circuit
2.7 Oscillation circuit
7470
7471
7477
7478
(1) Oscillation circuit using a ceramic resonator An oscillation circuit can be formed by connecting a ceramic resonator or a crystal oscillator between the XIN pin and the XOUT pin and between the XCIN pin and the XCOUT pin. Figure 2.7.1 shows an example of oscillation circuit using a ceramic resonator. Regarding such circuit constants as Rd, CIN and COUT, ask the oscillator maker for information and then set the recommended value.
7470/7477 group
XIN 14 XOUT 15 Rd XIN 19 (18)
7471/7478 group
XOUT 20 (19) Rd XCIN 23 (25) XCOUT 24 (26) Rd'
CIN
COUT
CIN
COUT
CCIN
CCOUT
Note: The number in parentheses denotes the case of a flat package.
Fig. 2.7.1 Example of Oscillation circuit using ceramic resonator
(2) External clock input To the main clock and timer clock oscillation circuits, clocks can also be supplied from the outside. Figure 2.7.2 shows an example of circuits in this case. At this time, make the XOUT (XCOUT) pin open. As an external clock to be input to the XIN (XCIN) pin, use a pulse signal with a duty ratio of 50 %.
7470/7477 group
XIN 14 XOUT 15 Open External oscillation circuit XIN 19 (18)
7471/7478 group
XOUT 20 (19) Rd XCOUT 24 (26) Open External oscillation circuit 23 (25) XCIN
VCC
CIN COUT
VCC VSS Duty ratio 50%
VSS Duty ratio 50%
Note: The number in parentheses denotes the case of a flat package.
Fig. 2.7.2 Example of external clock input circuit Note: The XCIN and the XCOUT pin are not provided in the 7470/7477 group.
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2.8 Low-power dissipation function
2.8 Low-power dissipation function
7470
7471
7477
7478
2.8.1 CPU mode register The CPU mode register consists of a stack page selection bit+1 and internal system clock control bits+2 . +1: In the products having a RAM capacity of 192 bytes or less, a RAM is not arranged on page 1, so this bit is not available. (Be sure to set this bit to "0.") +2: In the 7470/7477 group, which is not provided with a sub-clock (f(XCIN)) generating circuit, f(XCIN) is not used. (Be sure to set this bit to "0.") Figure 2.8.1 shows a structure of CPU mode register.
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
00
CPU mode register (CPUM) [Address 00FB16] B Name 0, 1 Fix these bits to "0." 2 Stack page selection bit Function At reset R W 0 0: In page 0 area 1: In page 1 area (Note 1) 0
3 4 5
Nothing is allocated for this bit. This is write enabled bit and is undefined at reading. P50, P51/XCIN,XCOUT selection bit XCOUT drive capacity selection bit 0: P50, P51 1: XCIN, XCOUT (Note 2) 0: Low 1: High (Note 2)
? 0 0 0
?!
6 Main clock (XIN-XOUT) 0: Oscillates stop bit 1: Stops (Note 2) 7 Internal system clock selection bit 0: XIN-XOUT selected (Ordinary mode) 1: XCIN-XCOUT selected (Low speed mode) (Note 2)
0
Notes 1: In the products having a RAM capacity of 192 bytes or less, set this bit to "0." 2: Since the 7470/7477 group is not provided with the sub-clock generating circuit, f(XCIN) cannot be used. Fix these bits to "0."
Fig. 2.8.1 Structure of CPU mode register
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APPLICATION
2.8 Low-power dissipation function
2.8.2 Application examples 7470 7471 7477 7478
As examples of application, examples of setting between modes are shown below. (1) (2) (3) (4) Ordinary mode Stop mode Ordinary mode Wait mode Ordinary mode Low speed Low speed mode Ordinary Ordinary mode Ordinary mode mode mode
Note: In the 7470/7477 group, which is not provided with a sub-clock generating circuit, the lowspeed mode is not available.
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2.8 Low-power dissipation function
(1) Ordinary mode Stop mode Ordinary mode 7470 7471 7477 7478
,
,
,
,
Specifications: The stop mode is executed by the STP instruction. Restoration to the ordinary mode is attained by INT0 interrupt. Figure 2.8.2 shows an example of control procedure.
Clear the timer 3 interrupt enable bit (timer 3 interrupt disabled) Clear the timer 4 interrupt enable bit (timer 4 interrupt disabled)
Stop the timer 3 and timer 4 and select the timer 3 count source (Set the Timer 34 mode register)
! ! ! ! 1 ! ! 1 T34M (Address 00F916) Select the timer 3 count source
Set the return interrupt source Clear the INT0 interrupt request bit Execute the NOP instruction Set the INT0 interrupt enable bit (INT0 interrupt enabled) Set the timer 3 and 4 count state (Set the Timer 34 mode register)
! ! ! ! 0 ! ! 0 T34M (Address 00F916) Timer 3 count Timer 4 count
Clear the interrupt disable flag (each interrupt enabled)
Execute the STP instruction
INT0 interrupt
RTI Set the interrupt disable flag (each interrupt disabled)
Re-set the timer 3 and 4 Timer 34 mode register Timer 3 register Timer 4 register
Clear the interrupt disable flag (each interrupt enabled)
Fig. 2.8.2 Example of control procedure [Ordinary mode Stop mode Ordinary mode]
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2.8 Low-power dissipation function
(2) Ordinary mode Wait mode Ordinary mode 7470 7471 7477 7478
Specifications: The wait mode is executed by the WIT instruction. Restoration to the ordinary mode is attained by INT0 interrupt. Figure 2.8.3 shows an example of control procedure.
Set the return interrupt source Clear the INT0 interrupt request bit Execute the NOP instruction Set the INT0 interrupt enable bit (INT0 interrupt enable)
Clear the interrupt disable flag (each interrupt enable)
Execute the WIT instruction
INT0 interrupt
RTI
The next address of the WIT instruction
Fig. 2.8.3 Example of control procedure [Ordinary mode Wait mode Ordinary mode]
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2.8 Low-power dissipation function
(3) Ordinary mode Low speed mode 7470 7471 7477 7478
x
x
Specifications: The system clock is switched from the main clock (f(XIN) = 8 MHz) to the subclock (f(XCIN) = 32 kHz). The main clock is stopped. Figure 2.8.4 shows an example of control procedure.
Set the CPU mode register
0 0 1 1 ! ! 0 0 CPUM (Address 00FB 16) Fixed to "0" XCIN, XCOUT selected XCOUT drive capacity High power selected Main clock oscillation System clock Ordinary mode selected
Wait f(XCIN) oscillation stabilizing time T For certain time, ask the oscillator manufacturer for information.
Set the CPU mode register
1 1 1 1 ! ! 0 0 CPUM (Address 00FB 16) Fixed to "0" XCIN, XCOUT selected XCOUT drive capacity High power selected Main clock stop System clock Low speed mode selected
Fig. 2.8.4 Example of control procedure [Ordinary mode Low speed mode]
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2.8 Low-power dissipation function
(4) Low speed mode Ordinary mode 7470 7471 7477 7478
x
x
Specifications: The system clock is switched from the sub-clock (f(XCIN) = 32 kHz) to the main clock (f(XIN) = 8 MHz). The sub-clock is stopped. Figure 2.8.5 shows an example of control procedure.
Set the CPU mode register
1 0 1 1 ! ! 0 0 CPUM (Address 00FB 16) Fixed to "0" XCIN, XCOUT selected XCOUT drive capacity High power selected Main clock oscillation System clock Low-speed mode selected
Wait f(XIN) oscillation stabilizing time T For certain time, ask the oscillator manufacturer.
Set the CPU mode register
0 0 ! 0 ! ! 0 0 CPUM (Address 00FB 16) Fixed to "0" P50, P51 selected Main clock oscillation System clock Ordinary mode selected
Fig. 2.8.5 Example of control procedure [Low speed mode Ordinary mode]
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2.8 Low-power dissipation function
2.8.3 Notes on use 7470 7471 7477 7478
2 For notes on use, refer to "1.17 Low-power dissipation function."
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APPLICATION
2.9 Countermeasures against noise
2.9 Countermeasures against noise
7470
7471
7477
7478
Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 2.9.1 Shortest wiring length The wiring on a printed circuit board can be as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) Wiring for the RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). Reason The reset works to initialize a microcomputer. The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway.
Noise
Reset circuit VSS
RESET VSS
Reset circuit VSS
RESET VSS
N.G.
7470/7471/ 7477/7478 group
O.K.
7470/7471/ 7477/7478 group
Fig. 2.9.1 Wiring for the RESET pin
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2.9 Countermeasures against noise
(2) Wiring for clock input/output pins 7470 7471 7477 7478
q Make the length of wiring which is connected to clock I/O pins as short as possible. q Make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. q Separate the VSS pattern only for oscillation from other VSS patterns. Reason A microcomputer's operation synchronizes with a clock generated by the oscillator (circuit). If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a malfunction or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer.
Noise
An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example
XIN XOUT VSS
XIN XOUT VSS
XIN XOUT VSS
N.G.
O.K.
Separate the VSS line for oscillation from other V SS lines
Fig. 2.9.2 Wiring for clock I/O pins
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APPLICATION
2.9 Countermeasures against noise
(3) Wiring for the VPP pin of the One Time PROM version and the EPROM version q Make the length of wiring which is connected to the VPP pin as short as possible. q Connect an approximately 5 k resistor to the VPP pin in serial. q The P33 pin is also used as the VPP pin. Reason The VPP pin of the One Time PROM and the EPROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current for wiring flow into the PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the built-in PROM, which may cause a program runaway. 7470 7471 7477 7478
7470/7471/7477/7478 group Approximately 5k P33/VPP
Fig. 2.9.3 Wiring for the VPP pin of the One Time PROM and the EPROM version
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2.9 Countermeasures against noise
2.9.2 Connection of a bypass capacitor across the Vss line and the Vcc line Connect an approximately 0.1 F bypass capacitor across the VSS line and the VCC line as follows: q Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. q Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. q Use lines with a larger diameter than other signal lines for VSS line and VCC line. 7470 7471 7477 7478
VCC
Chip Chip
VCC
VSS
VCC
VSS
2.9.3 Wiring to analog input pins q Connect an approximately 100 to 1 k resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. q Connect an approximately 1000 pF capacitor across the VSS pin and the analog input pin. Besides, connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog input pin and the VSS pin at equal length. Reason Signals which is input in an analog input pin (such as an A-D converter input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. If a capacitor between an analog input pin and the VSS pin is grounded at a position far away from the VSS pin, noise on the GND line may enter a microcomputer through the capacitor.
VSS
Fig. 2.9.4 Bypass capacitor across the VSS line and the VCC line
Noise
(Note) Microcomputer Analog input pin
Thermistor
N.G.
O.K.
VSS
Note : The resistor is for dividing resistance with a thermister.
Fig. 2.9.5 Analog signal line and a resistor and a capacitor
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2.9 Countermeasures against noise
2.9.4 Consideration for oscillator 7470 7471 7477 7478
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping an oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) Keeping an oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an osillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. Signal lines where potential levels change frequently (such as the CNTR pin line) may affect other lines at signal rising or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway.
Mutual inductance M Large current GND XIN XOUT VSS
Microcomputer
Fig. 2.9.6 Wiring for a large current signal line
Do not cross
CNTR XIN XOUT VSS
Fig. 2.9.7 Wiring to a signal line where potential levels change frequently
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2.9 Countermeasures against noise
2.9.5 Setup for I/O ports 7470 7471 7477 7478
Setup I/O ports using hardware and software as follows: q Connect a resistor of 100 or more to an I/O port in series. q As for an input port, read data several times by a program for checking whether input levels are equal or not. q As for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. q Rewrite data to direction registers and pull-up control registers (only the product having it) at fixed periods. When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse.
O.K.
Data bus
Direction register
Noise
Noise
N.G.
Port latch I/O port pins
Fig. 2.9.8 Setup for I/O ports
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APPLICATION
2.9 Countermeasures against noise
2.9.6 Providing of watchdog timer function by software 7470 7471 7477 7478
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. q Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N + 1 Q (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. q Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing count after the initial value N has been set. q Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following cases: If the SWDT contents do not change after interrupt processing. q Decrements the SWDT contents by 1 at each interrupt processing. q Determins that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed periods (at the fixed interrupt processing count). q Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: When the contents of the SWDT reach 0 or less by continuative decrement without initializing to the initial value N.
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APPLICATION
2.9 Countermeasures against noise
7470 7471 7477 7478
Main routine (SWDT) N CLI Main processing N (SWDT) =N? =N Interrupt processing routine errors
Interrupt processing routine (SWDT) (SWDT)--1 Interrupt processing >0 RTI Return Main routine errors
(SWDT) 0? 0
Fig. 2.9.9 Watchdog timer by software
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APPLICATION
2.10 Notes on programming
2.10 Notes on programming
7470
7471
7477
7478
2.10.1 Processor status register (1) Initialization of processor status register After a reset, the contents of the processor status register (PS) are undefined except for the I flag which is "1." Therefore, flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. (2) How to reference the processor status register To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S + 1). If necessary, execute the PLP instruction to return the PS to its original status. A NOP instruction should be executed after every PLP instruction.
Reset
Flags initializing
Main program
Fig. 2.10.1 Initialization of flags in PS
(S)
(S) + 1
Saved PS
Fig. 2.10.2 Stack memory contents after PHP instruction execution
PLP instruction
NOP instruction
Fig. 2.10.3 Note to execute by PLP instruction
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APPLICATION
2.10 Notes on programming
2.10.2 Decimal calculations 7470 7471 7477 7478
(1) Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal results in decimal mode. To calculate in decimal notation, set the decimal mode flag (D) to "1" with the SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, or CLD instruction. (2) Note on flags in decimal mode When decimal mode is selected, the values of three of the flags in the status register (the N, V, and Z flags) are invalid after a ADC or SBC instruction is executed. The Carry flag (C) is set to "1" if a carry is generated as a result of the calculation, or is cleared to "0" if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to "0" before each calculation. To check for a borrow, the C flag must be initialized before each calculation. 2 For other notes, refer to the notes described in each section.
Set D Flag to "1"
ADC or SBC instruction
NOP instruction
SEC, CLC, or CLD instruction
Fig. 2.10.4 Note for decimal operation
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APPLICATION
2.11 Differences between 7470/7471 group and 7477/7478 group
2.11 Differences between 7470/7471 group and 7477/7478 group
7470
7471
7477
7478
Table 2.11.1 shows differences between the 7470/7471 group and the 7477/7478 group. Exercise due care at substitution. Table 2.11.1 Differences between 7470/7471 group and 7477/7478 group 7470/7471 group RAM size ROM size 32-pin SOP Operating temperature range Interrupt source types Serial I/O Byte specification mode Port P2 Software pull-up control A-D conversion VREF OFF function 128/192/384 bytes 4K/8K/16K byte N -20 to 85C 12 Clock synchronous Y General I/O port / Analog input P0, P1, P2, P4, P5 Y 7477/7478 group 192/384 bytes (128/192/384 bytes for extended operating temperature version) 8K/16K byte (4K/8K/16K byte for extended operating temperature version) Y -20 to 85C (-40C to +85C for extended operating temperature version) 13 Clock synchronous / UART N General input port / Analog input P0, P1, P4, P5 N
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APPLICATION
2.12 Example of application circuit
2.12 Example of application circuit
7470
7471
7477
7478
x
x
x
Figures 2.12.1 and 2.12.2 show examples of application circuit using the 7470 group, the 7478 group respectively.
Power source for control (DC 5 V)
Power source (AC 100 V)
BCR
BCR
Blower motor
Brush motor
Zero cross detection
Key input
PORT
Dust sensor
Thermistor
Photo triac
Photo triac
Vcc
INT
AD
AD
PORT
M37470M2
PORT
LED Mode display Power display
ON/OFF
High
Fig. 2.12.1 Application circuit example (cleaner)
7470/7471/7477/7478 GROUP USER'S MANUAL
Low
Auto
PORT
ON/OFF
High
Low
Auto
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2-60
M5296JFP
Total power source IC Vcc
APPLICATION
M59300L
M
Air mix dumper control
Voltage stabilization circuit Watchdog timer RESET PORT
By direction motor driver M59300L By direction motor driver M59300L By direction motor driver
2.12 Example of application circuit
Temperature setting
M
Ventilation control
Air mix door opening
AD
M Suction control
M37478M4T
Insolation sensor
PWM
Sensor of outside car temperature
Driver
M
Blower motor control
Sensor of inside car temperature
Fig. 2.12.2 Application circuit example (Semi-auto air conditioner)
7470/7471/7477/7478 GROUP USER'S MANUAL
PORT
Evaporative sensor Display driver
UART
Key input
PORT
Temperature display
x
7470
Diagnosis
7471
x x
7477 7478
CHAPTER 3 APPENDIX
3.1 Control registers 3.2 Mask ROM ordering method 3.3 ROM programming ordering method 3.4 Mark specification form 3.5 Package outline 3.6 SFR memory map 3.7 Pin configuration
APPENDIX
3.1 Control registers
3.1 Control registers
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0,1,2,4) [Address 00C116, 00C316, 00C516, 00C916] B Name Function 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode
At reset
RW
0 Port Pi direction register 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
Notes 1: The 7477/7478 group is not provided with the port P2 direction register (input only). 2: The Port P4 is provided as below: *7470/7477 group has 2 bits of P4 0 and P41 *7471/7478 group has 4 bits of P4 0 to P43.
Fig. 3.1.1 Structure of Port Pi direction register (i=0, 1, 2, 4)
Port P0 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 pull-up control register [Address 00D016] B 0 1 2 3 4 5 6 7 Name Port P00 pull-up control bit Port P01 pull-up control bit Port P02 pull-up control bit Port P03 pull-up control bit Port P04 pull-up control bit Port P05 pull-up control bit Port P06 pull-up control bit Port P07 pull-up control bit Function 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up
At reset
RW
0 0 0 0 0 0 0 0
Fig. 3.1.2 Structure of Port P0 pull-up control register 3-2
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APPENDIX
3.1 Control registers
Ports P1 to P5 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Ports P1 to P5 pull-up control register [Address 00D116] b 0 1 2 3 4 5 6 7 Name Ports P10 to P13 pull-up control bit Ports P14 to P17 pull-up control bit Ports P20 to P23 pull-up control bit (Note 2) Function
At reset
RW
0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up 0 : No pull-up 1 : Pull-up Ports P24 to P27 pull-up 0 : No pull-up control bit (Notes 2, 3) 1 : Pull-up Ports P40 to P43 pull-up 0 : No pull-up control bit (Note 4) 1 : Pull-up Nothing is allocated for this bit. This is write disabled bit and is undefined at reading. Ports P50 to P53 pull-up 0 : No pull-up control bit (Note 3) 1 : Pull-up Nothing is allocated for this bit. This is write disabled bit and is undefined at reading.
0 0 0 0 0 ? 0 ? ?! ?!
Notes 1 : In the 7470/7477 group, the P1 to P4 Pull-up control register is provided. 2 : In the 7477/7478 group, nothing is allocated to these bits. They are undefined at reading. 3 : In the 7470/7477 group, nothing is allocated to these bits. They are undefined at reading. 4 : The 7470/7477 group is provided with only P40 and P41.
Fig. 3.1.3 Structure of Ports P1 to P5 pull-up control register
Edge polarity selection register
b7 b6 b5 b4 b3 b2 b1 b0
Edge polarity selection register (EG) [Address 00D416] Name 0 INT0 edge selection bit B 1 INT1 edge selection bit 2 CNTR0 edge selection bit 3 CNTR1 edge selection bit 4 CNTR0/CNTR1 interrupt selection bit Function 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : Falling edge 1 : Rising edge 0 : CNTR0 1 : CNTR1
At reset
RW
0 0 0 0 0
5 INT1 source selection 0 : P31/INT1 bit (at STP or WIT 1 : P00 to P07 "L" level input instruction execution) (for key-on wake-up) 6, 7 Nothing is allocated for these bits. These are write disabled bits and are undefined at reading.
0
?
?!
Fig. 3.1.4 Structure of Edge polarity selection register
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APPENDIX
3.1 Control registers
Input latch register
b7 b6 b5 b4 b3 b2 b1 b0
Input latch register (ILR) [Address 00D616] B Name Function
When b0 of EG (Note) is "0": reverse level on INT0 pin When b0 of EG (Note) is "1": level on INT0 pin
At reset
RW
0 P30/INT0 latch bit
?
!
1 P31/INT1 latch bit
When b1 of EG (Note) is "0": reverse level on INT1 pin When b1 of EG (Note) is "1": level on INT1 pin
?
!
2 P32/CNTR0 latch bit When b2 of EG (Note) is "0":
reverse level on CNTR0 pin When b2 of EG (Note) is "1": level on CNTR0 pin
?
!
3 P33/CNTR1 latch bit When b3 of EG (Note) is "0":
reverse level on CNTR1 pin When b3 of EG (Note) is "1": level on CNTR1 pin
?
!
4 Nothing is allocated for these bits. These to are write disabled bits and are undefined at 7 reading. Note: EG is the Edge polarity selection register.
?
?!
Fig. 3.1.5 Structure of Input latch register
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
0
A-D control register (ADCON) [Address 00D916] B 0 1 2 3 4 A-D conversion end bit (Note 2) VREF connection selection bit Name A-D input selection bits
0 0 0 0 1 1 1 1
b2 b1 b0
Function
0 0 1 1 0 0 1 1 0 : P20/IN0 1 : P21/IN1 0 : P22/IN2 1 : P23/IN3 0 : P24/IN4 1 : P25/IN5 0 : P26/IN6 1 : P27/IN7
At reset
RW
0 0
(Note 1)
0 1
0 : Under conversion 1 : End conversion 0 : The VREF pin is
separated from the comparison voltage VThe 7477/7478 group is not generator. provided with this bit. 1 : The VREF pin is This bit is undefined at connected to reset. comparison voltage generator.
0
Nothing is allocated for these bits. 5, 6 These are write disabled bits and are undefined at reading. 7 Fix this bit to "0."
? 0
?! 00
Notes 1: Since the 7470/7477 group is not provided with pins P24-P27, do not set. 2: *A-D conversion is started by setting bit 3 to "0." *Writing "0" into bit 3 is valid. Even if "1" is written into bit 3, this bit is not set to "1." Accordingly, when writing a value into the A-D control register without affecting bit 3, set bit 3 to "1."
Fig. 3.1.6 Structure of A-D control register 3-4
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.1 Control registers
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (AD) [Address 00DA16] B Function
At reset
RW !
0 This is a read-only register to store A-D to conversion results. 7
?
Fig. 3.1.7 Structure of A-D conversion register
Serial I/O mode register (7470/7471 group)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O mode register (SM) [Address 00DC16] B Name
b1 b0
Function
0 0 1 1 0 : f(XIN)/8 or f(XCIN)/8 1 : f(XIN)/16 or f(XCIN)/16 0 : f(XIN)/32 or f(XCIN)/32 1 : f(XIN)/512 or f(XCIN)/512 (Note)
At reset
RW
0, 1 Internal clock selection bits
0
2 3
Synchronous clock 0 : External clock selection bit 1 : Internal clock Serial I/O port selection bit SRDY signal output selection bit SRDY signal selection bit Serial I/O byte specify mode selection bit 0 : Ordinary I/O port (P15, P16) 1 : Serial I/O port (SOUT, CLK pin) 0 : Ordinary I/O port(P1 7) 1 : SRDY signal output pin 0 : SRDY signal 1 : SARDY signal 0 : Ordinary mode 1 : Byte specify mode
0 0 0 0 0 0
4 5 6 7
P15/SOUT, SRDY output 0 : CMOS output structure selection bit 1 : N-channel open-drain output
Note: Since the 7470 group is not provided with the sub-clock generating circuit, do not select f(XCIN).
Fig. 3.1.8 Structure of Serial I/O mode register
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APPENDIX
3.1 Control registers
Serial I/O register (7470/7471 group)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O register (SIO) [Address 00DD16] B Function
At reset
RW
0 At transmit: A value of "0016" to "FF16" can be to set as transmit data. 7 At the transmit, data is transmitted one bit at a time starting with the least significant bit. At receive: At the receive, data is received one bit at a time starting with the most significant bit.
?
Fig. 3.1.9 Structure of Serial I/O register
Serial I/O counter and Byte counter (7470/7471 group)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O counter and Byte counter [Address 00DE16] B Function 0 Byte counter to When using the byte specification mode, set 3 a value of "0016" to "0F16." Supposing that the value to be written into the byte counter is "n," a Serial transmit/receive is performed with the clock of the "n + 1"-th byte. 4 Serial I/O counter to When the internal clock is selected as a 6 synchronous clock, this counter generates 8 shift clocks. When transmit data is written into the Serial I/O register, "07 16" is set in the Serial I/O counter. 7 Nothing is allocated for this bit. This is write disabled bit and is undefined at reading.
At reset
RW
?
?
!
?
?!
Fig. 3.1.10 Structure of Serial I/O counter and Byte counter
3-6
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APPENDIX
3.1 Control registers
Transmit/receive buffer register (7477/7478 group)
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/receive buffer register (TB/RB) [Address 00E016] Function 0 At transmit: A value of "0016" to "FF16" can be set as transmit data. to The transmit data is transferred 7 automatically by writing the transmit data into the Transmit shift register. At receive: When all receive data has been input into the Receive shift register, the receive data is automatically transferred to the receive buffer register. B
At reset
RW
?
Fig. 3.1.11 Structure of Transmit/receive buffer register
Serial I/O status register (7477/7478 group)
b7 b6 b5 b4 b3 b2 b1 b0
1
Serial I/O status register (SIOSTS) [Address 00E116] B 0 1 2 3 4 5 6 7 Name Transmit buffer empty flag (TBE) Receive buffer full flag (RBF) Transmit shift completion flag (TSC) Overrun error flag (OE) Parity error flag (PE) Framing error flag (FE) Summing error flag (SE) Function 0 : Buffer full 1 : Buffer empty 0 : Buffer empty 1 : Buffer full
At reset
RW ! ! ! ! ! ! ! 1!
0 0 0 0 0 0 0 1
0 : Transmit shift in progress 1 : Transmit shift completed 0 : No error 1 : Overrun error 0 : No error 1 : Parity error 0 : No error 1 : Framing error 0 : (OE) U (PE) U (FE) = 0 1 : (OE) U (PE) U (FE) = 1 Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "1."
Fig. 3.1.12 Structure of Serial I/O status register
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APPENDIX
3.1 Control registers
Serial I/O control register (7477/7478 group)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register (SIOCON) [Address 00E216] B 0 1 Name BRG count source selection bit (CSS) Serial I/O synchronous clock selection bit (SCS) Function 0 : f(XIN)/4 or f(XCIN)/4 1 : f(XIN)/16 or f(XCIN)/16 *In clock synchronous mode 0 : BRG output divided by 4 1 : External clock input *In UART mode 0 : BRG output divided by 16 1 : External clock input divided by 16 0 : P17/SRDY pin operates as ordinary I/O pin 1 : P17/SRDY pin operates as SRDY output pin 0 : When transmit buffer has emptied 1 : When transmit shift operation is completed
At reset
RW
0
0
2 SRDY output enable bit (SRDY)
VIn the UART mode, this bit is invalid.
0
3
Transmit interrupt source selection bit (TIC)
0
4 5 6
Transmit enable bit (TE) 0 : Transmit disabled 1 : Transmit enabled Receive enable bit (RE) 0 : Receive disabled 1 : Receive enabled Serial I/O mode 0 : Clock asynchronous selection bit (SIOM) serial I/O (UART) 1 : Clock synchronous 0 : Serial I/O disabled
(pins operates as ordinary I/O pins P14-P17)
0 0 0
7 Serial I/O enable bit (SIOE)
0
1 : Serial I/O enabled (pins operates as serial I/O pins RXD - SRDY) (Note) Note: Port P14-P17 are operates as the serial I/O pin only when the serial I/O enable bit is "1" (enable state). At this time, Port P1 7 is also used as an ordinary I/O port. In the UART mode, port P1 6 is used as an ordinary I/O port when the internal clock is selected.
Fig. 3.1.13 Structure of Serial I/O control register
UART control register (7477/7478 group)
b7 b6 b5 b4 b3 b2 b1 b0
1111
UART control register (UARTCON) [Address 00E316] B Name Function 0: 8 bits 0 Character length selection bit (CHAS) 1: 7 bits 0: Parity checking disabled 1 Parity enable bit 1: Parity checking enabled (PARE) 0: Even parity 2 Parity selection bit (PARS) 1: Odd parity 3 Stop bit length 0: 1 stop bit selection bit (STPS) 1: 2 stop bits 4 Nothing is allocated for these bits. These are write to disabled bits. When these bits are read out, the 7 values are "1."
At reset
RW
0 0 0 0 1 1!
Fig. 3.1.14 Structure of UART control register
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APPENDIX
3.1 Control registers
Timers 1 to 4
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1, Timer 2, Timer 3, Timer 4 (T1, T2, T3, T4) [Address 00F016, 00F116, 00F216, 00F316] B Function
At reset
RW
0 *Set "0016 to FF16." to *The value is decremented by 1 each time a 7 count source is input. *Each Timer values are set to the respective counter. *The count values are read out by reading the respective timer. Note : Timers 1 and 2 are undefined. Timer 3 is "FF16." Timer 4 is "0716."
(Note)
Fig. 3.1.15 Structure of Timers 1 to 4
Timer FF register
b7 b6 b5 b4 b3 b2 b1 b0
Timer FF register (TF) [Address 00F716] B 0 1 2 to 7 Name Timer 1 division flip-flop Timer 4 division flip-flop Function 0 : Initial value is "0" 1 : Initial value is "1" 0 : Initial value is "0" 1 : Initial value is "1"
At reset
RW
0 0 ? ?!
Nothing is allocated for these bits. These are write disabled bits and are undefined at reading.
Fig. 3.1.16 Structure of Timer FF register
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APPENDIX
3.1 Control registers
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 12 mode register (T12M) [Address 00F816] B 0 Name Function 0 : Count start 1 : Count stop 0 : Internal clock (Note 1) 1 : P32/CNTR0 external clock 0 : f(XIN)/16 or f(XCIN)/16 1 : f(XCIN) (Note 2) 0 : P12 port output 1 : T0(Timer 1 overflow divided by 2) 0 : Count start 1 : Count stop 0 : Internal clock (Note 1) 1 : Timer 1 overflow signal
b7 b6
At reset
RW
Timer 1 count stop bit 1 Timer 1 count source selection bit 2 Timer 1 internal clock source selection bit P12/T0 port output selection bit
0 0 0
3
0 0 0
4 Timer 2 count stop bit 5 Timer 2 count source selection bit
6, 7 Timer 2 internal clock source selection bits 0 0 : f(XIN)/16 or f(XCIN)/16 0 1 : f(XIN)/64 or f(XCIN)/64 1 0 : f(XIN)/128 or f(XCIN)/128 1 1 : f(XIN)/256 or f(XCIN)/256 (Note 3)
0
Notes 1: In the 7470/7477 group, the internal clock is f(X IN)/16. 2: Since the 7470/7477 group is not provided the sub-clock generating circuit, f(XCIN) cannot be used. Fix this bit to "0." 3: Since the 7470/7477 group is not provided the sub-clock generating circuit, f(XCIN) cannot be used.
Fig. 3.1.17 Structure of Timer 12 mode register
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 34 mode register (T34M) [Address 00F916] B 0 Name Function 0 : Count start 1 : Count stop
b2 b1
At reset
RW
Timer 3 count stop bit 1, 2 Timer 3 count source selection bits
0
0 0 : f(XIN)/16 or f(XCIN)/16 0 1 : f(XCIN) 1 0 : Timer 1 overflow or
Timer 2 overflow
1 1 : P33/CNTR1 external
0
clock 3 Timer 4 count stop bit 0 : Count start 1 : Count stop
b4 b3
(Note 2) 0
4, 5 Timer 4 count source selection bits
0 0 : Timer 3 overflow 0 1 : f(XIN)/16 or f(XCIN)/16 1 0 : Timer 1 overflow or
0
Timer 2 overflow 1 1 : P33/CNTR1 external clock (Notes 1, 2) 6 Timer 4 pulse width measurement mode selection bit P13/T1 port output selection bit 0 : Timer mode 1 : External pulse width measurement mode 0 : P13 port 1 : T1(Timer 4 overflow divided
by 2 or PWM output)
0
7
0
Notes 1: When Timer 1 overflow is selected as a Timer 2 count source, the Timer 4 count source is the Timer 1 overflow regardless of the value of bit 6 of the Timer mode register 2. 2: Since the 7470/7477 group is not provided the sub-clock generating circuit, f(X CIN) cannot be used.
Fig. 3.1.18 Structure of Timer 34 mode register
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APPENDIX
3.1 Control registers
Timer mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer mode register 2 (TM2) [Address 00FA16] B 0 Name Function
At reset
RW
Timer 1 overflow FF 0 : Set disable set enable bit 1 : Set enable 0 : Set disable 1 Timer 4 overflow FF set enable bit 1 : Set enable Nothing is allocated for these bits. These are 2 to write disabled bits and are undefined at reading. 5 6 7 Timer 3, timer 4 count overflow signal selection bit Timer 3, timer 4 function selection bit 0 : Timer 1 overflow 1 : Timer 2 overflow 0 : Ordinary mode 1 : PWM mode
0 0 ? ?!
0 0
Fig. 3.1.19 Structure of Timer mode register 2
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
00
CPU mode register (CPUM) [Address 00FB16] Name Fix these bits to "0." 0, 1 2 Stack page selection bit B Function At reset R W 0 0: In page 0 area 1: In page 1 area (Note 1) 0
3 4 5
Nothing is allocated for this bit. This is write enabled bit and is undefined at reading. P50, P51/XCIN,XCOUT selection bit XCOUT drive capacity selection bit 0: P50, P51 1: XCIN, XCOUT (Note 2) 0: Low 1: High (Note 2)
? 0 0 0
?!
6 Main clock (XIN-XOUT) 0: Oscillates stop bit 1: Stops (Note 2) 7 Internal system clock selection bit 0: XIN-XOUT selected (Ordinary mode) 1: XCIN-XCOUT selected (Low speed mode) (Note 2)
0
Notes 1: In the products having a RAM capacity of 192 bytes or less, set this bit to "0." 2: Since the 7470/7477 group is not provided with the sub-clock generating circuit, f(XCIN) cannot be used. Fix these bits to "0."
Fig. 3.1.20 Structure of CPU mode register
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APPENDIX
3.1 Control registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IR1) [Address 00FC16] B 0 1 2 3 4 5 Name Function
At reset
RW V V V V ?! V
0 : No interrupt request Timer 1 interrupt 1 : Interrupt requested request bit Timer 2 interrupt 0 : No interrupt request request bit 1 : Interrupt requested 0 : No interrupt request Timer 3 interrupt 1 : Interrupt requested request bit Timer 4 interrupt 0 : No interrupt request request bit 1 : Interrupt requested Nothing is allocated for this bit. This is write disabled bit and is undefined at reading. Serial I/O receive interrupt request bit (7477/7478 group)(Note) Serial I/O interrupt request bit (7470/7471group) Serial I/O transmit interrupt request bit (7477/7478 group) A-D conversion completion interrupt request bit 0 : No interrupt request 1 : Interrupt requested 0 : No interrupt request 1 : Interrupt requested
0 0 0 0 ?
0
6
0
V
7
0 : No interrupt request 1 : Interrupt requested
0
V
Note: In the 7470/7471group, nothing is allocated for bit 5. This is write disabled bit and is undefined at reading. V : "0" is set by software, but not "1."
Fig. 3.1.21 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IR2) [Address 00FD16] B 0 Name Function
At reset
RW V V V ?!
INT0 interrupt request 0 : No interrupt request 1 : Interrupt requested bit 1 INT1 interrupt request 0 : No interrupt request bit 1 : Interrupt requested 0 : No interrupt request 2 CNTR0 or CNTR1 interrupt request bit 1 : Interrupt requested 3 Nothing is allocated for these bits. There are write to disabled bits and are undefined at reading. 7 V : "0" is set by software, but not "1."
0 0 0 ?
Fig. 3.1.22 Structure of Interrupt request register 2
3-12
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.1 Control registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (IE1) [Address 00FE16] B 0 1 2 3 4 5 Name Function
At reset
RW
0 : Interrupt disabled Timer 1 interrupt 1 : Interrupt enabled enable bit Timer 2 interrupt 0 : Interrupt disabled enable bit 1 : Interrupt enabled 0 : Interrupt disabled Timer 3 interrupt 1 : Interrupt enabled enable bit Timer 4 interrupt 0 : Interrupt disabled enable bit 1 : Interrupt enabled Nothing is allocated for this bit. This is write disabled bit and is undefined at reading. Serial I/O receive interrupt enable bit (7477/7478 group) (Note) Serial I/O interrupt enable bit (7470/7471 group) Serial I/O transmit interrupt enable bit (7477/7478 group) A-D conversion completion interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
0 0 0 0 ?
0
?!
6
0
7
0 : Interrupt disabled 1 : Interrupt enabled
0
Note: In the 7470/7471 group, Nothing is allocated for bit 5. This is write disabled bit and undefined at reading.
Fig. 3.1.23 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (IE2) [Address 00FF16] B 0 Name Function
At reset
RW
0 : Interrupt disabled INT0 interrupt enable 1 : Interrupt enabled bit 1 INT1 interrupt enable 0 : Interrupt disabled bit 1 : Interrupt enabled 0 : Interrupt disabled 2 CNTR0 or CNTR1 interrupt enable bit 1 : Interrupt enabled 3 Nothing is allocated for these bits. There are write to disabled bits and are undefined at reading. 7
0 0 0 ? ?!
Fig. 3.1.24 Structure of Interrupt control register 2
7470/7471/7477/7478 GROUP USER'S MANUAL
3-13
APPENDIX
3.2 Mask ROM ordering method
3.2 Mask ROM ordering method
GZZ-SH02-91B<9YA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37470M2-XXXSP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM EPROM type (indicate the type used)
(hexadecimal notation)
27128
EPROM address 000016 Area for ASCII 000F16 001016 2FFF16 300016
ROM (4K) codes of the name of the product `M37470M2-'
27256
EPROM address 000016 Area for ASCII 000F16 001016 6FFF16 700016
ROM (4K) codes of the name of the product `M37470M2-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 EFFF16 F00016
ROM (4K) codes of the name of the product `M37470M2-'
3FFF16
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37470M2-' to addresses 000016 to 000F16. ASCII codes `M37470M2-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `0' = 3016 `M' = 4D16 `2' = 3216
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-14
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH02-91B<9YA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37470M2-XXXSP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27128 g= .BYTE $C000 `M37470M2-' 27256 g = $8000 .BYTE `M37470M2-' 27512 g = $0000 .BYTE `M37470M2-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. g 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (32P4B for M37470M2-XXXSP) and attach to the mask ROM confirmation form.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-15
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH02-92B<9YA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37470M4-XXXSP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM EPROM type (indicate the type used)
(hexadecimal notation)
27128
EPROM address 000016 Area for ASCII 000F16 001016 1FFF16 200016
ROM (8K) codes of the name of the product `M37470M4-'
27256
EPROM address 000016 Area for ASCII 000F16 001016 5FFF16 600016
ROM (8K) codes of the name of the product `M37470M4-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 DFFF16 E00016
ROM (8K) codes of the name of the product `M37470M4-'
3FFF16
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37470M4-' to addresses 000016 to 000F16. ASCII codes `M37470M4-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `0' = 3016 `M' = 4D16 `4' = 3416
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-16
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH02-92B<9YA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37470M4-XXXSP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27128 g= .BYTE $C000 `M37470M4-' 27256
g = $8000 .BYTE `M37470M4-'
27512
g = $0000 .BYTE `M37470M4-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (32P4B for M37470M4-XXXSP) and attach to the mask ROM confirmation form.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-17
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH02-93B<9YA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37470M8-XXXSP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM EPROM type (indicate the type used)
(hexadecimal notation)
27256
EPROM address 000016 Area for ASCII 000F16 001016 3FFF16 400016
ROM (16K) codes of the name of the product `M37470M8-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016
ROM (16K) codes of the name of the product `M37470M8-'
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37470M8-' to addresses 000016 to 000F16. ASCII codes `M37470M8-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `0' = 3016 `M' = 4D16 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-18
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH02-93B<9YA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37470M8-XXXSP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27256 g = $8000 .BYTE `M37470M8-' 27512 g = $0000 .BYTE `M37470M8-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (32P4B for M37470M8-XXXSP) and attach to the mask ROM confirmation form.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-19
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH02-94B<9YB0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37471M2-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Microcomputer name : M37471M2-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37471M2-XXXFP (hexadecimal notation)
27128
EPROM address 000016 Area for ASCII 000F16 001016 2FFF16 300016
ROM (4K) codes of the name of the product `M37471M2-'
27256
EPROM address 000016 Area for ASCII 000F16 001016 6FFF16 700016
ROM (4K) codes of the name of the product `M37471M2-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 EFFF16 F00016
ROM (4K) codes of the name of the product `M37471M2-'
3FFF16
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37471M2-' to addresses 000016 to 000F16. ASCII codes `M37471M2-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `1' = 3116 `M' = 4D16 `2' = 3216
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-20
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH02-94B<9YB0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37471M2-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27128 g= .BYTE $C000 `M37471M2-' 27256 g = $8000 .BYTE `M37471M2-' 27512
g = $0000 .BYTE `M37471M2-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. g 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (42P4B for M37471M2-XXXSP, 56P6N for M37471M2-XXXFP) and attach to the mask ROM confirmation form.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-21
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH02-95B<9YB0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37471M4-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Microcomputer name : M37471M4-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37471M4-XXXFP (hexadecimal notation)
27128
EPROM address 000016 Area for ASCII 000F16 001016 1FFF16 200016
ROM (8K) codes of the name of the product `M37471M4-'
27256
EPROM address 000016 Area for ASCII 000F16 001016 5FFF16 600016
ROM (8K) codes of the name of the product `M37471M4-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 DFFF16 E00016
ROM (8K) codes of the name of the product `M37471M4-'
3FFF16
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37471M4-' to addresses 000016 to 000F16. ASCII codes `M37471M4-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `1' = 3116 `M' = 4D16 `4' = 3416
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-22
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH02-95B<9YB0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37471M4-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27128 g= .BYTE $C000 `M37471M4-' 27256 g = $8000 .BYTE `M37471M4-' 27512
g = $0000 .BYTE `M37471M4-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (42P4B for M37471M4-XXXSP, 56P6N for M37471M4-XXXFP) and attach to the mask ROM confirmation form.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-23
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH02-96B<9YB0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37471M8-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based in this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Microcomputer name : M37471M8-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37471M8-XXXFP (hexadecimal notation)
27256
EPROM address 000016 Area for ASCII 000F16 001016 3FFF16 400016
ROM (16K) codes of the name of the product `M37471M8-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016
ROM (16K) codes of the name of the product `M37471M8-'
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37471M8-' to addresses 000016 to 000F16. ASCII codes `M37471M8-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `1' = 3116 `M' = 4D16 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-24
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH02-96B<9YB0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37471M8-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27256 g = $8000 .BYTE `M37471M8-' 27512 g = $0000 .BYTE `M37471M8-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (42P4B for M37471M8-XXXSP, 56P6N for M37471M8-XXXFP) and attach to the mask ROM confirmation form.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-25
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH08-22B<3ZA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37477M2TXXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37477M2TXXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37477M2TXXXFP (hexadecimal notation)
27128
EPROM address 000016 000F16 001016 2FFF16 300016
data ROM 4096 bytes Product name ASCII code : `M37477M2T'
27256
EPROM address 000016 000F16 001016 6FFF16 700016
data ROM 4096 bytes Product name ASCII code : `M37477M2T'
27512
EPROM address 000016 000F16 001016 EFFF16 F00016
data ROM 4096 bytes Product name ASCII code : `M37477M2T'
3FFF16
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M37477M2T" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `7' = 3716 `M' = 4D16 `2' = 3216
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` T ' = 5416 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-26
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH08-22B<3ZA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37477M2TXXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27128 g = $C000 .BYTE `M37477M2T' 27256 g = $8000 .BYTE `M37477M2T' 27512
g = $0000 .BYTE `M37477M2T'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (32P4B for M37477M2TXXXSP, 32P2W for M37477M2TXXXFP) and attach it to the mask ROM confirmation form.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-27
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-67B<2XA1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37477M4-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37477M4-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37477M4-XXXFP (hexadecimal notation)
27128
EPROM address 000016 000F16 001016 1FFF16 200016
data ROM 8192 bytes Product name ASCII code : `M37477M4-'
27256
EPROM address 000016 000F16 001016 5FFF16 600016
data ROM 8192 bytes Product name ASCII code : `M37477M4-'
27512
EPROM address 000016 000F16 001016 DFFF16 E00016
data ROM 8192 bytes Product name ASCII code : `M37477M4-'
3FFF16
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M37477M4-" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `7' = 3716 `M' = 4D16 `4' = 3416
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-28
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-67B<2XA1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37477M4-XXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27128 g= .BYTE $C000 `M37477M4-' 27256 g = $8000 .BYTE `M37477M4-' 27512
g = $0000 .BYTE `M37477M4-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (32P4B for M37477M4-XXXSP, 32P2W for M37477M4-XXXFP) and attach it to the mask ROM confirmation form.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-29
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-73B<2XA1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37477M4TXXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37477M4TXXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37477M4TXXXFP (hexadecimal notation)
27128
EPROM address 000016 000F16 001016 1FFF16 200016
data ROM 8192 bytes Product name ASCII code : `M37477M4T'
27256
EPROM address 000016 000F16 001016 5FFF16 600016
data ROM 8192 bytes Product name ASCII code : `M37477M4T'
27512
EPROM address 000016 000F16 001016 DFFF16 E00016
data ROM 8192 bytes Product name ASCII code : `M37477M4T'
3FFF16
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M37477M4T" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `7' = 3716 `M' = 4D16 `4' = 3416
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` T ' = 5416 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-30
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-73B<2XA1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37477M4TXXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27128 g= .BYTE $C000 `M37477M4T' 27256 g = $8000 .BYTE `M37477M4T' 27512
g = $0000 .BYTE `M37477M4T'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (32P4B for M37477M4TXXXSP, 32P2W for M37477M4TXXXFP) and attach it to the mask ROM confirmation form.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-31
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-68B<2XA1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37477M8-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37477M8-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37477M8-XXXFP (hexadecimal notation)
27256
EPROM address 000016 000F16 001016 3FFF16 400016
data ROM 16384 bytes Product name ASCII code : `M37477M8-'
27512
EPROM address 000016 000F16 001016 BFFF16 C00016
data ROM 16384 bytes Product name ASCII code : `M37477M8-'
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M37477M8-" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `7' = 3716 `M' = 4D16 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-32
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-68B<2XA1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37477M8-XXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27256 g = $8000 .BYTE `M37477M8-' 27512 g = $0000 .BYTE `M37477M8-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (32P4B for M37477M8-XXXSP, 32P2W for M37477M8-XXXFP) and attach it to the mask ROM confirmation form.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-33
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-74B<2XA1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37477M8TXXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37477M8TXXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37477M8TXXXFP (hexadecimal notation)
27256
EPROM address 000016 000F16 001016 3FFF16 400016
data ROM 16384 bytes Product name ASCII code : `M37477M8T'
27512
EPROM address 000016 000F16 001016 BFFF16 C00016
data ROM 16384 bytes Product name ASCII code : `M37477M8T'
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M37477M8T" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `7' = 3716 `M' = 4D16 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` T ' = 5416 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-34
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-74B<2XA1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37477M8TXXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27256 g = $8000 .BYTE `M37477M8T' 27512 g = $0000 .BYTE `M37477M8T'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (32P4B for M37477M8TXXXSP, 32P2W for M37477M8TXXXFP) and attach it to the mask ROM confirmation form.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-35
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH08-23B<2XA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37478M2TXXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37478M2TXXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37478M2TXXXFP (hexadecimal notation)
27128
EPROM address 000016 000F16 001016 2FFF16 300016
data ROM 4096 bytes Product name ASCII code : `M37478M2T'
27256
EPROM address 000016 000F16 001016 6FFF16 700016
data ROM 4096 bytes Product name ASCII code : `M37478M2T'
27512
EPROM address 000016 000F16 001016 EFFF16 F00016
data ROM 4096 bytes Product name ASCII code : `M37478M2T'
3FFF16
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M37478M2T" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `8' = 3816 `M' = 4D16 `2' = 3216
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` T ' = 5416 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-36
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH08-23B<2XA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37478M2TXXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27128 g= .BYTE $C000 `M37478M2T' 27256 g = $8000 .BYTE `M37478M2T' 27512
g = $0000 .BYTE `M37478M2T'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (42P4B for M37478M2TXXXSP, 56P6N for M37478M2TXXXFP) and attach it to the mask ROM confirmation form.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-37
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-70B<2XA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37478M4-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37478M4-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37478M4-XXXFP (hexadecimal notation)
27128
EPROM address 000016 000F16 001016 1FFF16 200016
data ROM 8192 bytes Product name ASCII code : `M37478M4-'
27256
EPROM address 000016 000F16 001016 5FFF16 600016
data ROM 8192 bytes Product name ASCII code : `M37478M4-'
27512
EPROM address 000016 000F16 001016 DFFF16 E00016
data ROM 8192 bytes Product name ASCII code : `M37478M4-'
3FFF16
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M37478M4-" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `8' = 3816 `M' = 4D16 `4' = 3416
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-38
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-70B<2XA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37478M4-XXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27128 g= .BYTE $C000 `M37478M4-' 27256 g = $8000 .BYTE `M37478M4-' 27512
g = $0000 .BYTE `M37478M4-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (42P4B for M37478M4-XXXSP, 56P6N for M37478M4-XXXFP) and attach it to the mask ROM confirmation form.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-39
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-76B<2XA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37478M4TXXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37478M4TXXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37478M4TXXXFP (hexadecimal notation)
27128
EPROM address 000016 000F16 001016 1FFF16 200016
data ROM 8192 bytes Product name ASCII code : `M37478M4T'
27256
EPROM address 000016 000F16 001016 5FFF16 600016
data ROM 8192 bytes Product name ASCII code : `M37478M4T'
27512
EPROM address 000016 000F16 001016 DFFF16 E00016
data ROM 8192 bytes Product name ASCII code : `M37478M4T'
3FFF16
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M37478M4T" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `8' = 3816 `M' = 4D16 `4' = 3416
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` T ' = 5416 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-40
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-76B<2XA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37478M4TXXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27128 g = $C000 .BYTE `M37478M4T' 27256 g = $8000 .BYTE `M37478M4T' 27512
g = $0000 .BYTE `M37478M4T'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (42P4B for M37478M4TXXXSP, 56P6N for M37478M4TXXXFP) and attach it to the mask ROM confirmation form.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-41
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-71B<2XA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37478M8-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37478M8-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37478M8-XXXFP (hexadecimal notation)
27256
EPROM address 000016 000F16 001016 3FFF16 400016
data ROM 16384 bytes Product name ASCII code : `M37478M8-'
27512
EPROM address 000016 000F16 001016 BFFF16 C00016
data ROM 16384 bytes Product name ASCII code : `M37478M8-'
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M37478M8-" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `8' = 3816 `M' = 4D16 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-42
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-71B<2XA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37478M8-XXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27256 g = $8000 .BYTE `M37478M8-' 27512 g = $0000 .BYTE `M37478M8-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (42P4B for M37478M8-XXXSP, 56P6N for M37478M8-XXXFP) and attach it to the mask ROM confirmation form.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-43
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-77B<2XA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37478M8TXXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37478M8TXXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37478M8TXXXFP (hexadecimal notation)
27256
EPROM address 000016 000F16 001016 3FFF16 400016
data ROM 16384 bytes Product name ASCII code : `M37478M8T'
27512
EPROM address 000016 000F16 001016 BFFF16 C00016
data ROM 16384 bytes Product name ASCII code : `M37478M8T'
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M37478M8T" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `8' = 3816 `M' = 4D16 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` T ' = 5416 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-44
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.2 Mask ROM ordering method
GZZ-SH06-77B<2XA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37478M8TXXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program. EPROM type The pseudo-command 27256 g = $8000 .BYTE `M37478M8T' 27512 g = $0000 .BYTE `M37478M8T'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (42P4B for M37478M8TXXXSP, 56P6N for M37478M8TXXXFP) and attach it to the mask ROM confirmation form.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-45
APPENDIX
3.3 ROM programming ordering method
3.3 ROM programming ordering method
GZZ-SH03-60B<06A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37470E4-XXXSP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM EPROM type (indicate the type used)
(hexadecimal notation)
27128
EPROM address 000016 Area for ASCII 000F16 001016 1FFF16 200016
ROM (8K) codes of the name of the product `M37470E4-'
27256
EPROM address 000016 Area for ASCII 000F16 001016 5FFF16 600016
ROM (8K) codes of the name of the product `M37470E4-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 DFFF16 E00016
ROM (8K) codes of the name of the product `M37470E4-'
3FFF16
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37470E4-' to addresses 000016 to 000F16. ASCII codes `M37470E4-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `0' = 3016 `E' = 4516 `4' = 3416
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-46
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APPENDIX
3.3 ROM programming ordering method
GZZ-SH03-60B<06A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37470E4-XXXSP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27128 g= .BYTE $C000 `M37470E4-' 27256 g= .BYTE $8000 `M37470E4-' 27512
g= .BYTE
$0000 `M37470E4-'
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer).
g 3. Comments
(2/2)
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3-47
APPENDIX
3.3 ROM programming ordering method
GZZ-SH02-97B<9YA0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37470E8-XXXSP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM EPROM type (indicate the type used)
(hexadecimal notation)
27256
EPROM address 000016 Area for ASCII 000F16 001016 3FFF16 400016
ROM (16K) codes of the name of the product `M37470E8-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016
ROM (16K) codes of the name of the product `M37470E8-'
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37470E8-' to addresses 000016 to 000F16. ASCII codes `M37470E8-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `0' = 3016 `E' = 4516 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-48
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APPENDIX
3.3 ROM programming ordering method
GZZ-SH02-97B<9YA0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37470E8-XXXSP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27256 g= .BYTE $8000 `M37470E8-' 27512 g= .BYTE $0000 `M37470E8-'
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer).
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-49
APPENDIX
3.3 ROM programming ordering method
GZZ-SH03-59B<06B0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37471E4-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Microcomputer name : M37471E4-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37471E4-XXXFP (hexadecimal notation)
27128
EPROM address 000016 Area for ASCII 000F16 001016 1FFF16 200016
ROM (8K) codes of the name of the product `M37471E4-'
27256
EPROM address 000016 Area for ASCII 000F16 001016 5FFF16 600016
ROM (8K) codes of the name of the product `M37471E4-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 DFFF16 E00016
ROM (8K) codes of the name of the product `M37471E4-'
3FFF16
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37471E4-' to addresses 000016 to 000F16. ASCII codes `M37471E4-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `1' = 3116 `E' = 4516 `4' = 3416
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-50
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.3 ROM programming ordering method
GZZ-SH03-59B<06B0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37471E4-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27128 g= .BYTE $C000 `M37471E4-' 27256 g= .BYTE $8000 `M37471E4-' 27512
g= .BYTE
$0000 `M37471E4-'
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for M37471E4-XXXSP or the 56P6N Mark Specification Form the M37471E4-XXXFP.
g 3. Comments
(2/2)
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3-51
APPENDIX
3.3 ROM programming ordering method
GZZ-SH02-98B<9YB0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37471E8-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Microcomputer name : M37471E8-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37471E8-XXXFP (hexadecimal notation)
27256
EPROM address 000016 Area for ASCII 000F16 001016 3FFF16 400016
ROM (16K) codes of the name of the product `M37471E8-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016
ROM (16K) codes of the name of the product `M37471E8-'
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37471E8-' to addresses 000016 to 000F16. ASCII codes `M37471E8-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `1' = 3116 `E' = 4516 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-52
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.3 ROM programming ordering method
GZZ-SH02-98B<9YB0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37471E8-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27256 g = $8000 .BYTE `M37471M8-' 27512 g = $0000 .BYTE `M37471M8-'
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37471E8-XXXSP or the 56P6N Mark Specification Form for the M37471E8-XXXFP.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-53
APPENDIX
3.3 ROM programming ordering method
GZZ-SH06-79B<2XA1>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37477E8-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37477E8-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37477E8-XXXFP (hexadecimal notation)
27256
EPROM address 000016 000F16 001016 3FFF16 400016
data ROM 16384 bytes Product name ASCII code : `M37477E8-'
27512
EPROM address 000016 000F16 001016 BFFF16 C00016
data ROM 16384 bytes Product name ASCII code : `M37477E8-'
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M37477E8-" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `7' = 3716 `E' = 4516 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-54
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.3 ROM programming ordering method
GZZ-SH06-79B<2XA1>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37477E8-XXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27256 g= .BYTE $8000 `M37477E8-' 27512 g= .BYTE $0000 `M37477E8-'
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation, the ROM will not be processed.
g 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37477E8-XXXSP or the 32P2W Mark Specification Form for the M37477E8-XXXFP.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-55
APPENDIX
3.3 ROM programming ordering method
GZZ-SH06-83B<2XA1>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37477E8TXXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37477E8TXXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37477E8TXXXFP (hexadecimal notation)
27256
EPROM address 000016 000F16 001016 3FFF16 400016
data ROM 16384 bytes Product name ASCII code : `M37477E8T'
27512
EPROM address 000016 000F16 001016 BFFF16 C00016
data ROM 16384 bytes Product name ASCII code : `M37477E8T'
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M37477E8T" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `7' = 3716 `E' = 4516 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` T ' = 5416 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-56
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.3 ROM programming ordering method
GZZ-SH06-83B<2XA1>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37477E8TXXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27256 g= .BYTE $8000 `M37477E8T' 27512 g= .BYTE $0000 `M37477E8T'
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation, the ROM will not be processed.
g 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37477E8TXXXSP or the 32P2W Mark Specification Form for the M37477E8TXXXFP.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-57
APPENDIX
3.3 ROM programming ordering method
GZZ-SH06-81B<2XA0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37478E8-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37478E8-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37478E8-XXXFP (hexadecimal notation)
27256
EPROM address 000016 000F16 001016 3FFF16 400016
data ROM 16384 bytes Product name ASCII code : `M37478E8-'
27512
EPROM address 000016 000F16 001016 BFFF16 C00016
data ROM 16384 bytes Product name ASCII code : `M37478E8-'
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M37478E8-" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `8' = 3816 `E' = 4516 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-58
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.3 ROM programming ordering method
GZZ-SH06-81B<2XA0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37478E8-XXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27256 g= .BYTE $8000 `M37478E8-' 27512 g= .BYTE $0000 `M37478E8-'
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM will not be processed.
g 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37478E8-XXXSP or the 56P6N Mark Specification Form for the M37478E8-XXXFP.
g 3. Comments
(2/2)
7470/7471/7477/7478 GROUP USER'S MANUAL
3-59
APPENDIX
3.3 ROM programming ordering method
GZZ-SH06-85B<2XA0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37478E8TXXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37478E8TXXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37478E8TXXXFP (hexadecimal notation)
27256
EPROM address 000016 000F16 001016 3FFF16 400016
data ROM 16384 bytes Product name ASCII code : `M37478E8T'
27512
EPROM address 000016 000F16 001016 BFFF16 C00016
data ROM 16384 bytes Product name ASCII code : `M37478E8T'
7FFF16
FFFF16
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M37478E8T" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `7' = 3716 `8' = 3816 `E' = 4516 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` T ' = 5416 FF16 FF16 FF16 FF16 FF16 FF16 FF16
(1/2)
3-60
7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.3 ROM programming ordering method
GZZ-SH06-85B<2XA0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37478E8TXXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27256 g = $8000 .BYTE `M37478E8T' 27512 g = $0000 .BYTE `M37478E8T'
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM will not be processed.
g 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37478E8TXXXSP or the 56P6N Mark Specification Form for the M37478E8TXXXFP.
g 3. Comments
(2/2)
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3-61
APPENDIX
3.4 Mark specification form
3.4 Mark specification form
32P4B (32-PIN SHRINK DIP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark #2 !7
Mitsubishi lot number (6-digit or 7-digit)
Mitsubishi IC catalog name
q
!6
B. Customer's Parts Number + Mitsubishi catalog name #2 !7 Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name
Mitsubishi lot number (6-digit or 7-digit)
q !6
Note1 : 2: 3: 4:
The mark field should be written right aligned. The fonts and size of characters are standard Mitsubishi type. Customer's Parts Number can be up to 16 characters : Only 0 ~ 9, A ~ Z, +, -, /, (, ), &, (c), (periods), and (commas) are usable. If the Mitsubishi logo is not required, check the box on the right. Mitsubishi logo is not required
.
,
C. Special Mark Required #2 !7
q
!6
Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the upper figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer's trade mark logo must be used in the Special Mark, check the Special logo required box on the right. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. 3 : The standard Mitsubishi font is used for all characters except for a logo.
3-62
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APPENDIX
3.4 Mark specification form
32P2W-A (32-PIN SOP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark #2 !7
Mitsubishi IC catalog name Mitsubishi IC catalog name Mitsubishi lot number (6-digit or 7-digit)
q
!6
B. Customer's Parts Number + Mitsubishi catalog name #2 !7 Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer's Parts Number can be up to 13 characters : Only 0 ~ 9, A ~ Z, +, -, /, (, ), &, (c), (periods), (commas) are usable. 4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required
Mitsubishi lot number (6-digit or 7-digit)
.
,
q
!6
C. Special Mark Required #2 !7 Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer's trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required
q
!6
3 : The standard Mitsubishi font is used for all characters except for a logo.
7470/7471/7477/7478 GROUP USER'S MANUAL
3-63
APPENDIX
3.4 Mark specification form
42P4B (42-PIN SHRINK DIP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark $2 @2
Mitsubishi lot number (6-digit or 7-digit)
Mitsubishi IC catalog name
q
@1
B. Customer's Parts Number + Mitsubishi catalog name $2 @2 Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name
Mitsubishi lot number (6-digit or 7-digit)
q @1
Note1 : 2: 3: 4:
The mark field should be written right aligned. The fonts and size of characters are standard Mitsubishi type. Customer's Parts Number can be up to 15 characters : Only 0 ~ 9, A ~ Z, +, -, /, (, ), &, (c), (periods), and (commas) are usable. If the Mitsubishi logo is not required, check the box on the right. Mitsubishi logo is not required
.
,
C. Special Mark Required $2 @2
q
@1
Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the upper figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer's trade mark logo must be used in the Special Mark, check the Special logo required box on the right. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. 3 : The standard Mitsubishi font is used for all characters except for a logo.
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7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.4 Mark specification form
56P6N-A (56-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark $5 $4 @9 @8 Mitsubishi IC catalog name
Mitsubishi lot number (6-digit or 7-digit)
%6
q
!6
!7
B. Customer's Parts Number + Mitsubishi IC catalog name $4 @9 Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name and Mitsubishi lot number Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer's Parts Number can be up to 11 characters : Only 0 ~ 9, A ~ Z, +, -, /, (, ), &, (c),. (period), and (comma) are usable. 4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required
$5
@8
,
%6
q
!6
!7
5 : Arrangement of Mitsubishi IC catalog name and Mitsubishi lot number is dependent on number of Mitsubishi IC catalog name and that Mitsubishi logo is required or not. C. Special Mark Required $5 $4 @9 @8 Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer's trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required
%6
q
!6
!7
3 : The standard Mitsubishi font is used for all characters except for a logo. 7470/7471/7477/7478 GROUP USER'S MANUAL
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APPENDIX
3.4 Mark specification form
SHRINK DIP MARK SPECIFICATION FORM for One Time PROM version microcomputers
Enter the catalog number of the microcomputer for which this mark specification is intended. (If you do not know the ROM code number, enter XXX in its place.) The catalog number of the microcomputer
M
A. Standard Mitsubishi Mark Customer specified part number will be printed together with the ROM code number on the top line. Enter the desired part number left aligned in the box below. (up to 10 characters)
Note2 :
RXXX
Mitsubishi catalog name (blank model number before writing) Mitsubishi lot number (6-digit or 7-digit)
Note1 : The following characters can be used in the part number : Uppercase alphabet, numbers, ampersand, hyphen, period, comma, +, /, (, ), (c) ((c) will be printed at 1.5 x character width) 2 : XXX is the ROM code number. B. Special Mark Required If you desire anything other than the standard Mitsubishi mark, it will be treated as a special mark. Special marks will take longer to produce and should be avoided if possible. If a special mark is to be printed, indicate the desired layout of the mark in the figure below. The layout will be duplicated as closely as possible.
Note1 : If the customer's trademark logo must be used in the Special Mark, please submit a clean original logo. Note that special marks require extra cost and time to produce.
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7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.5 Package outline
3.5 Package outline
7470/7471/7477/7478 GROUP USER'S MANUAL
3-67
APPENDIX
3.5 Package outline
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7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.6 SFR memory map
3.6 SFR memory map
Figure 3.6.1 shows the special function register (SFR) memory map.
00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16
Port P0 Port P0 direction register Port P1 Port P1 direction register Port P2 Port P2 direction register (Note 1) Port P3 Port P4 Port P4 direction register Port P5 (Note 2)
Port P0 pull-up control register
Port P1-P5 pull-up control register (Note 3)
Edge polarity selection register Input latch register
A-D control register A-D conversion register Serial I/O mode register Serial I/O register Serial I/O counter Byte counter
(Note 4)
00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16
Transmit/receive buffer register Serial I/O status register Serial I/O control register UART control register Baud rate generator
(Note 5)
Timer 1 Timer 2 Timer 3 Timer 4
Timer FF register Timer 12 mode register Timer 34 mode register Timer mode register 2 CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2
Notes 1: In the 7477/7478 group, this register is not located. 2: In the 7470/7477 group, this register is not located. 3: This address is allocated P1-P4 pull-up control register for the 7470/7477 group. 4: In the 7477/7478 group, this register is not located. 5: In the 7470/7471 group, this register is not located.
Fig. 3.6.1 SFR memory map
7470/7471/7477/7478 GROUP USER'S MANUAL
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APPENDIX
3.7 Pin configuration
3.7 Pin configuration
Figures 3.7.1 to 3.7.4 show the pin configuration of 7470/7471/7477/7478 group.
P17/SRDY P16/CLK P15/SOUT P14/SIN P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4
32 31 30 29
5 6 7 8 9 10 11 12 13 14 15 16
28 27 26 25 24 23 22 21 20 19 18 17
P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0 RESET VCC
M37470M8-XXXSP M37470E8-XXXSP
Outline
32P4B (Note)
Note: The M37470M2-XXXSP and M37470M4/E4-XXXSP are included in the 32P4B package. All of these products are pin-compatible.
Fig. 3.7.1 Pin configuration of 7470 group
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7470/7471/7477/7478 GROUP USER'S MANUAL
APPENDIX
3.7 Pin configuration
P53 P17/SRDY P16/CLK P15/SOUT P14/SIN P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0
RESET
M37471M8-XXXSP M37471E8-XXXSP M37471E8SS
38 34
P51/XCOUT P50/XCIN VCC
Outline
42P4B (Note 1) 42S1B-A (M37471E8SS)
43
42
44
39
35
40
36
32
31
30
41
37
33
29
NC P04 P03 P02 P01 P00 P43 P42 P41 P40 NC P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0 NC
NC P05 P06 P07 P52 NC VSS P53 P17/SRDY P16/CLK P15/SOUT NC
45 46 47 48 49 50 51 52 53 54 55 56 10 12 13 14 15 11 16 3 4 2 1 6 7 8 5 9
28 27 26 25 24
RESET
M37471M8-XXXFP M37471E8-XXXFP
23 22 21 20 19 18 17
NC P51/XCOUT P50/XCIN NC VCC VSS AVSS NC XOUT XIN NC
NC P14/SIN P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF NC
Outline
56P6N-A (Note 2)
NC: No connection
Notes 1 :The M37471M2-XXXSP and M37471M4/E4-XXXSP are included in the 42P4B package. All of these products are pin-compatible. 2 :The M37471M2-XXXFP and M37471M4/E4-XXXFP are included in the 56P6N-A package. All of these products are pin-compatible. 3 :The only differences between the 42P4B package product and the 56P6N-A package product are package shape, absolute maximum ratings and the fact that the 56P6N-A package product has an AVSS pin.
Fig. 3.7.2 Pin configuration of 7471 group
7470/7471/7477/7478 GROUP USER'S MANUAL
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APPENDIX
3.7 Pin configuration
P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4
32 31 30 29
5 6 7 8 9 10 11 12 13 14 15 16
28 27 26 25 24 23 22 21 20 19 18 17
P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0
RESET
M37477M8-XXXSP M37477E8-XXXSP M37477M8TXXXSP M37477E8TXXXSP
VCC
Outline
32P4B (Note 1)
P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4
32 31 30 29
5 6 7 8 9 10 11 12 13 14 15 16
28 27 26 25 24 23 22 21 20 19 18 17
P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0
RESET
M37477M8-XXXFP M37477E8-XXXFP M37477M8TXXXFP M37477E8TXXXFP
VCC
Outline
32P2W-A (Note 2)
Notes 1 : The M37477M2TXXXSP, M37477M4-XXXSP and M37477M4TXXXSP are included in the 32P4B package. These products are pin-compatible. 2 : The M37477M2TXXXFP, M37477M4-XXXFP and M37477M4TXXXFP are included in the 32P2W-A package. These products are pin-compatible. 3 : The only differences between the 32P4B package product and the 32P2W-A package product are package shape and absolute maximum ratings.
Fig. 3.7.3 Pin configuration of 7477 group
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APPENDIX
3.7 Pin configuration
P53 P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS Outline
1 2 3 4 5 6 7
42 41 40 39 38 37 36
8 9 10 11 12 13 14 15 16 17 18 19 20 21
35 34 33 32 31 30 29 28 27 26 25 24 23 22
P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0
RESET
42P4B (Note 1) 42S1B-A (M37478E8SS)
41
37
33
43
39
35
31
42
38
34
44
40
36
32
30
29
NC P04 P03 P02 P01 P00 P43 P42 P41 P40 NC P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0 NC
M37478M8-XXXSP M37478E8-XXXSP M37478M8TXXXSP M37478E8TXXXSP M37478E8SS
P51/XCOUT P50/XCIN VCC
NC P05 P06 P07 P52 NC VSS P53 P17/SRDY P16/SCLK P15/TXD NC
45 46 47 48 49 50 51 52 53 54 55 56 10 14 12 13 11 15 16 3 4 2 1 6 7 8 5 9
28 27 26 25
RESET
M37478M8-XXXFP M37478E8-XXXFP M37478M8TXXXFP M37478E8TXXXFP
24 23 22 21 20 19 18 17
NC P51/XCOUT P50/XCIN NC VCC VSS AVSS NC XOUT XIN NC
NC P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF NC Outline 56P6N-A (Note 2)
NC: No connection
Notes1 : The M37478M2TXXXSP, M37478M4-XXXSP and M37478M4TXXXSP are included in the 42P4B package. These products are pin-compatible 2 : The M37478M2TXXXFP, M37478M4-XXXFP and M37478M4TXXXFP are included in the 56P6N-A package. These products are pin-compatible 3 : The only differences between the 42P4B package product and the 56P6N-A package product are package shape, absolute maximum ratings and the fact that the 56P6N-A package product has anAVSS pin.
Fig. 3.7.4 Pin configuration of 7478 group
7470/7471/7477/7478 GROUP USER'S MANUAL
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MITSUBISHI SEMICONDUCTORS USER'S MANUAL 7470/7471/7477/7478 Group
November First Edition 1996 Editioned by Committee of editing of Mitsubishi Semiconductor USER'S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation.
(c)1996 MITSUBISHI ELECTRIC CORPORATION
User's Manual 7470/7471/7477/7478 Group
Printed in Japan (ROD) (c) 1996 MITSUBISHI ELECTRIC CORPORATION.
New publication, effective November, 1996. Specifications subject to change without notice.

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